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    Semiconductor structures and manufacturing methods
    1.
    发明授权
    Semiconductor structures and manufacturing methods 有权
    半导体结构及制造方法

    公开(公告)号：US06605860B1

    公开(公告)日：2003-08-12

    申请号：US09597442

    申请日：2000-06-20

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    IPC分类号： H01L2906

    CPC分类号： H01L21/28202 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/31658 ,  H01L27/10864 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S257/905

    摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

    摘要翻译： 一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。 沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。 在侧壁上形成基本均匀的氮化硅层。 具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅 具有比<110>平面上的厚度大于超过<100>平面的厚度。 对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分 在氮化硅材料的下面部分上的<110>面上的二氧化硅。 选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。 然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

    Semiconductor structures and manufacturing methods
    2.
    发明授权
    Semiconductor structures and manufacturing methods 有权
    半导体结构及制造方法

    公开(公告)号：US06740555B1

    公开(公告)日：2004-05-25

    申请号：US09408248

    申请日：1999-09-29

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    IPC分类号： H01L218242

    CPC分类号： H01L21/28202 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/31658 ,  H01L27/10864 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S257/905

    摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

    摘要翻译： 一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。 沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。 在侧壁上形成基本均匀的氮化硅层。 具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅， 厚度大于<100>平面上的厚度。 对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分 在氮化硅材料的下面部分上的<110>面上的二氧化硅。 选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。 然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

    Integrated circuit trench device with a dielectric collar stack, and method of forming thereof
    3.
    发明授权
    Integrated circuit trench device with a dielectric collar stack, and method of forming thereof 失效
    具有介质套管叠层的集成电路沟槽器件及其形成方法

    公开(公告)号：US06486024B1

    公开(公告)日：2002-11-26

    申请号：US09577102

    申请日：2000-05-24

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Ulrike Gruening

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Ulrike Gruening

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861

    摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

    摘要翻译： 一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。 第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。 优选地，TEOS工艺和LOCOS工艺都用于形成第一层。 第二层优选是形成在氧化物层上的氮化硅层（114）。 多层用作沟槽的隔离环叠层。 第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

    Method of forming a vertically oriented device in an integrated circuit
    4.
    发明授权
    Method of forming a vertically oriented device in an integrated circuit 有权
    在集成电路中形成垂直取向器件的方法

    公开(公告)号：US06426253B1

    公开(公告)日：2002-07-30

    申请号：US09576465

    申请日：2000-05-23

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

    摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

    摘要翻译： 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

    Integrated circuit vertical trench device and method of forming thereof
    5.
    发明授权
    Integrated circuit vertical trench device and method of forming thereof 有权
    集成电路垂直沟槽器件及其形成方法

    公开(公告)号：US06335247B1

    公开(公告)日：2002-01-01

    申请号：US09597389

    申请日：2000-06-19

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

    IPC分类号： H01L21336

    CPC分类号： H01L27/10864 ,  H01L27/10876

    摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

    摘要翻译： 一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。 虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

    Self-aligned buried strap for vertical transistors
    8.
    发明授权
    Self-aligned buried strap for vertical transistors 有权
    用于垂直晶体管的自对准埋地带

    公开(公告)号：US06555862B1

    公开(公告)日：2003-04-29

    申请号：US09670745

    申请日：2000-09-27

    申请人： Jack A. Mandelman ,  Ulrike Gruening ,  Alexander Michaelis

    发明人： Jack A. Mandelman ,  Ulrike Gruening ,  Alexander Michaelis

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10876

    摘要： A semiconductor device formed by a method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, and depositing a dopant rich material on the buried strap. A trench top dielectric is formed on the dopant rich material, and portions of the dopant rich material are removed above the trench top dielectric. Dopants are outdiffused from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate.

    摘要翻译： 通过根据本发明的用于对准带扩散的方法形成的半导体器件包括以下步骤：在衬底中提供沟槽，所述沟槽具有形成在其中的存储节点，所述存储节点包括位于存储节点顶部的掩埋带，以及 在掩埋带上沉积富掺杂材料。 在富掺杂材料上形成沟槽顶部电介质，并且在沟槽顶部电介质上方去除部分富掺杂材料。 通过在沟槽的上部形成栅极以使得带扩散相对于栅极可操作地设置，掺杂剂从掺杂剂富的材料向外扩散到衬底的相邻区域中以形成带扩散。

    Trench capacitor with pillar
    10.
    发明申请
    Trench capacitor with pillar 审中-公开
    带支柱的沟槽电容器

    公开(公告)号：US20050048715A1

    公开(公告)日：2005-03-03

    申请号：US10651392

    申请日：2003-08-29

    申请人： Thomas Rupp ,  Stephan Kudelka ,  Alexander Michaelis ,  Carl Radens

    发明人： Thomas Rupp ,  Stephan Kudelka ,  Alexander Michaelis ,  Carl Radens

    IPC分类号： H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/945 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/66181

    摘要： A trench capacitor having a conductive pillar in a central region of a trench. A first plate of the capacitor includes the substrate in the lower portion of the trench and the conductive pillar. The capacitor dielectric is disposed over the conductive pillar and the sidewalls of the trench lower portion. A second plate of the capacitor is a conductive material disposed over the dielectric material. The conductive pillar increases the surface area of the capacitor plates, increasing the capacitance of the capacitor. A top portion of the conductive pillar may be hollow, further increasing the surface area of the capacitor plates.

    摘要翻译： 一种在沟槽的中心区域具有导电柱的沟槽式电容器。 电容器的第一板包括沟槽下部的基片和导电柱。 电容器电介质设置在导电柱和沟槽下部的侧壁之上。 电容器的第二板是设置在电介质材料上的导电材料。 导电柱增加电容器板的表面积，增加电容器的电容。 导电柱的顶部可以是中空的，进一步增加电容器板的表面积。