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71 条记录 (耗时 0.038 秒)

    Semiconductor devices and methods of forming the same
    61.
    发明申请
    Semiconductor devices and methods of forming the same 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20100207184A1

    公开(公告)日：2010-08-19

    申请号：US12658154

    申请日：2010-02-03

    申请人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

    发明人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

    摘要： A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other.

    摘要翻译： 半导体器件包括交替层叠在衬底上的绝缘图案和栅极图案; 衬底上的有源图案，其沿绝缘图案和栅极图案的侧壁向上延伸; 插入在栅极图案和活动图案之间的数据存储图案; 以及设置在相互邻近的一对栅极图案之间的有源图案中的源极/漏极区域。

    Nonvolatile memory device and method of making the same
    63.
    发明授权
    Nonvolatile memory device and method of making the same 有权
    非易失存储器件及其制造方法

    公开(公告)号：US08916926B2

    公开(公告)日：2014-12-23

    申请号：US13310407

    申请日：2011-12-02

    申请人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： H01L27/115 ,  G11C16/04 ,  H01L29/792

    CPC分类号： H01L27/1157 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

    摘要翻译： 非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及 介于导电材料层和支柱之间的信息存储膜。 在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。 在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE
    65.
    发明申请
    OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件的操作方法

    公开(公告)号：US20120195125A1

    公开(公告)日：2012-08-02

    申请号：US13315523

    申请日：2011-12-09

    申请人： BYEONG-IN CHOE ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： BYEONG-IN CHOE ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11582

    摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

    摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。 对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线 多个第一选择线。

    NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME
    66.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME 有权
    非易失存储器件及其制造方法

    公开(公告)号：US20120140562A1

    公开(公告)日：2012-06-07

    申请号：US13310407

    申请日：2011-12-02

    申请人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： Byeong-In Choe ,  Sunil Shim ,  Sung-Hwan Jang ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： G11C16/04 ,  H01L29/78

    CPC分类号： H01L27/1157 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

    摘要翻译： 非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及 介于导电材料层和支柱之间的信息存储膜。 在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。 在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

    Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same
    67.
    发明申请
    Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same 有权
    非易失性存储器件，其擦除方法和包括其的存储器系统

    公开(公告)号：US20120120740A1

    公开(公告)日：2012-05-17

    申请号：US13295335

    申请日：2011-11-14

    申请人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    发明人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

    摘要翻译： 公开了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。 所述擦除方法包括将地电压施加到与所述多个单元串的接地选择晶体管相连的接地选择线; 对与所述多个单元串的选择晶体管连接的串选择线施加接地电压; 对与多个单元串的存储单元相连的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

    Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices
    69.
    发明申请
    Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices 有权
    制造三维半导体器件及相关器件的方法

    公开(公告)号：US20110151667A1

    公开(公告)日：2011-06-23

    申请号：US12963241

    申请日：2010-12-08

    申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC分类号： H01L21/768

    CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

    摘要翻译： 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

    Three-dimensional non-volatile memory devices having highly integrated string selection and sense amplifier circuits therein
    70.
    发明授权
    Three-dimensional non-volatile memory devices having highly integrated string selection and sense amplifier circuits therein 有权
    其中具有高度集成的串选择和读出放大器电路的三维非易失性存储器件

    公开(公告)号：US08654584B2

    公开(公告)日：2014-02-18

    申请号：US13114790

    申请日：2011-05-24

    申请人： Kinam Kim ,  Yongjik Park ,  Siyoung Choi ,  Hyoungsub Kim ,  Jaehoon Jang

    发明人： Kinam Kim ,  Yongjik Park ,  Siyoung Choi ,  Hyoungsub Kim ,  Jaehoon Jang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

    摘要： Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括半导体衬底上的电绝缘层和电绝缘层的上表面上的非易失性存储单元的NAND型串。 NAND型非易失性存储单元串包括在电绝缘层上并列设置的多个垂直堆叠的非易失性存储单元子串。 提供串选择晶体管，其包括在电绝缘层和半导体衬底之间延伸的栅极电极以及半导体衬底中的源极和漏极区域。 提供接地选择晶体管，其包括在电绝缘层和半导体衬底之间延伸的栅电极以及半导体衬底中的源极和漏极区域。