公开(公告)号：US20150054556A1

公开(公告)日：2015-02-26

申请号：US14311831

申请日：2014-06-23

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。 信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US20140211576A1

公开(公告)日：2014-07-31

申请号：US13753800

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C29/08

CPC classification number: G11C29/36 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2029/1204

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个m个驱动器都耦合到m个位线中的对应的一个，其中m个驱动器各自包括写入一个电路和写入零电路。 响应于耦合到写入一个电路的第一控制信号并且响应于耦合到写入的第二控制信号将全零写入位单元行中，m个驱动器可操作以将所有的一个写入一行位单元 零电路。

公开(公告)号：US20140211572A1

公开(公告)日：2014-07-31

申请号：US13753771

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C11/22 ,  G11C11/401 ,  G11C14/0072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。 与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

公开(公告)号：US20140211533A1

公开(公告)日：2014-07-31

申请号：US13753814

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhanshu Khanna ,  Steven Craig Bartling

IPC: G11C11/22

CPC classification number: G11C11/221

Abstract: A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.

Abstract translation: 片上系统（SoC）提供了自参考非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 耦合到节点Q的钳位电路。第一读取电容器经由由第一控制信号控制的传输装置耦合到位线。 通过由第二控制信号控制的另一转移装置耦合到位线的第二读电容器。 感测放大器耦合在第一读取电容器和第二读取电容器之间。

公开(公告)号：US20140210535A1

公开(公告)日：2014-07-31

申请号：US13753819

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G11C11/2275 ,  G11C11/419 ,  G11C14/0072 ,  H03K3/356104

Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.

Abstract translation: 片上系统（SoC）包括配置为在较低电源电压下操作的一个或多个核心逻辑块和配置为在较高电源电压下工作的存储器阵列。 存储器中的每个位单元具有串联连接在第一板线和第二板线之间以形成节点Q的两个铁电电容器。通过激活写驱动器将数据位电压传送到节点Q以提供数据位电压响应 到较低的电源电压。 通过激活耦合到所选位单元的节点Q的读出放大器，在节点Q上升高数据位电压，使得感测放大器感测节点Q上的数据位电压，并且响应于增加节点上的数据位电压 Q到更高的电源电压。

公开(公告)号：US20140210511A1

公开(公告)日：2014-07-31

申请号：US13753856

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.

Abstract translation: 片上系统（SoC）具有耦合到一个或多个核心逻辑块的n行m列的非易失性存储器阵列。 M被限制为奇数。 每次写入一行m个数据位时，使用m个数据位来计算奇偶校验。 在存储奇偶校验位之前，它被反转。 每次读取一行时，检查奇偶校验以确定恢复的数据位中是否存在奇偶校验错误。 当检测到奇偶校验错误时，在SoC上执行引导操作。

公开(公告)号：US20140075233A1

公开(公告)日：2014-03-13

申请号：US13770448

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Abstract translation: 处理设备的设计和操作可配置为在非易失性存储器恢复机器状态期间优化唤醒时间和峰值功耗成本。 处理装置包括被配置为存储由处理装置的多个易失性存储元件表示的机器状态的多个非易失性逻辑元件阵列。 将存储的机器状态从多个非易失性逻辑元件阵列读出到多个易失性存储元件。 在制造期间，非易失性逻辑元件阵列中每行的数行和数位数是基于目标唤醒时间和峰值功率成本的。 在另一种方法中，可以并行，顺序地或以任何组合来对数据进行数据写入或读取数据，以优化操作特性。

公开(公告)号：US20140075232A1

公开(公告)日：2014-03-13

申请号：US13769963

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Abstract translation: 检测处理装置的输入电源质量。 响应于检测到不良的电力质量，输入功率被断开，并且处理设备使用可用的存储电荷来备份非易失性逻辑单元阵列中的机器状态。 当电源恢复时，存储的机器状态从非易失性逻辑单元阵列恢复到易失性逻辑元件，由此处理设备从紧接在功率损耗之前的状态恢复其处理，允许跨间歇电源的无缝处理。

公开(公告)号：US08472236B2

公开(公告)日：2013-06-25

申请号：US13626531

申请日：2012-09-25

Applicant: Texas Instruments Incorporated

Inventor： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

IPC: G11C11/22

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.