公开(公告)号：US11069773B2

公开(公告)日：2021-07-20

申请号：US16572357

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh

IPC: H01L29/06 ,  H01L29/788 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66

Abstract: A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate, the STI region bordering an active region in the semiconductor substrate; forming a plurality of gate structures over the semiconductor substrate; and forming a plurality of conductive contacts between the gate structures and in contact with the STI region, wherein a portion of the active region is between the conductive contacts.

公开(公告)号：US11031294B2

公开(公告)日：2021-06-08

申请号：US16102140

申请日：2018-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

公开(公告)号：US10784270B2

公开(公告)日：2020-09-22

申请号：US16051721

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US10665595B2

公开(公告)日：2020-05-26

申请号：US15903770

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: G06F17/50 ,  H01L27/11 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39 ,  G06F30/398

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US20200058665A1

公开(公告)日：2020-02-20

申请号：US16574220

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66 ,  H01L21/321 ,  H01L21/033 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/762

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.

公开(公告)号：US20200027846A1

公开(公告)日：2020-01-23

申请号：US16587867

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US20200013790A1

公开(公告)日：2020-01-09

申请号：US16574247

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L21/28 ,  H01L21/768 ,  H01L29/788 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/49 ,  H01L29/08 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/321

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US20200006466A1

公开(公告)日：2020-01-02

申请号：US16273260

申请日：2019-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having isolation structures therein and a capacitor structure located on a top surface of the isolation structure. The capacitor structure comprises a semiconductor material pattern and an insulator pattern inlaid in the semiconductor material pattern. The semiconductor material pattern and the insulator pattern are located at a same horizontal level on the isolation structure.

公开(公告)号：US10134644B2

公开(公告)日：2018-11-20

申请号：US15782588

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/8238 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US09887302B2

公开(公告)日：2018-02-06

申请号：US15346501

申请日：2016-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chieh-Chih Chou ,  Chih-Wen Hsiung ,  Kong-Beng Thei

IPC: H01L29/872 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A Schottky barrier diode is provided, which includes a semiconductor substrate, a first well region, an isolation region, a silicide layer and a silicon oxide-containing layer. The first well region of a first conductivity type is in the semiconductor substrate. The isolation region is in the first well region. The silicide layer is laterally adjacent to the isolation region, and over and in contact with the first well region. The silicon oxide-containing layer is over and in contact with the isolation region.