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    SEMICONDUCTOR STRUCTURE
    61.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20240389332A1

    公开(公告)日：2024-11-21

    申请号：US18780425

    申请日：2024-07-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Shih-Lien Linus Lu ,  Chia-En Huang ,  Yih Wang ,  Yu-Ming Lin

    IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L23/522

    Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

    Method of operating an integrated circuit and integrated circuit
    62.
    发明授权
    Method of operating an integrated circuit and integrated circuit 有权

    公开(公告)号：US12148465B2

    公开(公告)日：2024-11-19

    申请号：US18295154

    申请日：2023-04-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Shih-Lien Linus Lu

    IPC: G06F21/44 ,  G06F21/75 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/419

    Abstract: An integrated circuit includes a first memory cell array and a controller. The first memory cell array includes a first array of volatile memory cells having a first retention data time. The controller is coupled to the first memory cell array. The controller is configured to write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into, read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on, and determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

    Memory device and method of forming the same
    63.
    发明授权
    Memory device and method of forming the same 有权

    公开(公告)号：US12137569B2

    公开(公告)日：2024-11-05

    申请号：US18162642

    申请日：2023-01-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Shih-Lien Linus Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young

    IPC: H10B51/20 ,  H01L29/24 ,  H10B43/20 ,  H10B51/10 ,  H10B51/30

    Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

    Integrated circuit device and methods
    69.
    发明授权
    Integrated circuit device and methods 有权

    公开(公告)号：US11915787B2

    公开(公告)日：2024-02-27

    申请号：US17815113

    申请日：2022-07-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Bo-Feng Young ,  Yu-Ming Lin ,  Shih-Lien Linus Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chia-En Huang ,  Yih Wang

    IPC: G11C7/12 ,  G06F30/39 ,  G11C8/08

    CPC classification number: G11C7/12 ,  G06F30/39 ,  G11C8/08

    Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

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