公开(公告)号：US20050274984A1

公开(公告)日：2005-12-15

申请号：US11152411

申请日：2005-06-15

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshiaki Saito ,  Minoru Amano ,  Shigeki Takahashi ,  Tatsuya Kishi ,  Yoshihisa Iwata

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Yoshiaki Saito ,  Minoru Amano ,  Shigeki Takahashi ,  Tatsuya Kishi ,  Yoshihisa Iwata

IPC分类号： H01L27/105 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L21/76895 ,  H01L43/08

摘要： A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.

公开(公告)号：US20050141262A1

公开(公告)日：2005-06-30

申请号：US10845403

申请日：2004-05-14

申请人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

发明人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

IPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/404 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/105 ,  H01L27/12

CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

摘要翻译： 半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。 多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域 形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域 夹住通道体。

公开(公告)号：US20050083745A1

公开(公告)日：2005-04-21

申请号：US10981508

申请日：2004-11-05

申请人： Tatsuya Kishi ,  Minoru Amano ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Yoshihisa Iwata

发明人： Tatsuya Kishi ,  Minoru Amano ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Yoshihisa Iwata

IPC分类号： G11C11/16 ,  G11C7/00

CPC分类号： G11C11/16

摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

摘要翻译： 磁存储器包括：具有磁记录层的磁阻效应元件; 在磁阻效应元件上或其下方沿第一方向延伸的第一写入布线，布线的轴向横截面的重心与重心处的厚度中心分开，并且重心偏向 磁阻效应元件; 以及写入电路，其被配置为使电流通过所述第一写入布线，以便通过所述电流产生的磁场将信息记录在所述磁记录层中。

公开(公告)号：US06831855B2

公开(公告)日：2004-12-14

申请号：US10345188

申请日：2003-01-16

申请人： Tatsuya Kishi ,  Minoru Amano ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Yoshihisa Iwata

发明人： Tatsuya Kishi ,  Minoru Amano ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Yoshihisa Iwata

IPC分类号： G11C1100

CPC分类号： G11C11/16

摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

摘要翻译： 磁存储器包括：具有磁记录层的磁阻效应元件; 在磁阻效应元件上或其下方沿第一方向延伸的第一写入布线，布线的轴向横截面的重心与重心处的厚度中心分开，并且重心偏向 磁阻效应元件; 以及写入电路，其被配置为使电流通过所述第一写入布线，以便通过所述电流产生的磁场将信息记录在所述磁记录层中。

公开(公告)号：US06807094B2

公开(公告)日：2004-10-19

申请号：US10769757

申请日：2004-02-03

申请人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

发明人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

IPC分类号： G11C1115

CPC分类号： G11C11/16

摘要： A magnetic memory includes a magnetoresistance effect element having a magnetic recording layer, a first wiring extending in a first direction on or below the magnetoresistance effect element, a covering layer provided on at least both sides of the first wiring, and a writing circuit configured to pass a current through the first wiring in order to record information in the magnetic recording layer by a magnetic field generated by the current. The covering layer is made of magnetic material and has a uniaxial anisotropy in the first direction, along which a magnetization of the covering layer occurs.

摘要翻译： 磁存储器包括具有磁记录层的磁阻效应元件，在磁阻效应元件上或其下方沿第一方向延伸的第一布线，设置在第一布线的至少两侧的覆盖层，以及写入电路， 通过第一布线传递电流，以便通过电流产生的磁场将信息记录在磁记录层中。 覆盖层由磁性材料制成，并且在第一方向上具有单轴各向异性，沿着该方向发生覆盖层的磁化。

公开(公告)号：US06795334B2

公开(公告)日：2004-09-21

申请号：US10180024

申请日：2002-06-27

申请人： Yoshihisa Iwata ,  Yoshiaki Asao ,  Keiji Hosotani ,  Junichi Miyamoto

发明人： Yoshihisa Iwata ,  Yoshiaki Asao ,  Keiji Hosotani ,  Junichi Miyamoto

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C11/5607

摘要： A read blocks are connected to a read bit line. The read block has MTJ elements connected in series or in parallel, or arranged by combining series and parallel connections between the read bit line and a ground terminal. The MTJ elements are stacked on a semiconductor substrate. The read bit line is arranged on the MTJ elements stacked. A write word line extending in the X-direction and a write bit line extending in the Y-direction are present near the MTJ elements in the read block.

摘要翻译： 一个读块连接到读位线。 读块具有串联或并联连接的MTJ元件，或通过组合读位线与接地端之间的串联和并联连接进行排列。 MTJ元件堆叠在半导体衬底上。 读取位线被布置在堆叠的MTJ元件上。 在读取块中的MTJ元素附近存在沿X方向延伸的写字线和在Y方向上延伸的写位线。

公开(公告)号：US06278149B1

公开(公告)日：2001-08-21

申请号：US09146191

申请日：1998-09-03

申请人： Wataru Sato ,  Yoshiaki Asao

发明人： Wataru Sato ,  Yoshiaki Asao

IPC分类号： H01L31119

CPC分类号： H01L27/10894 ,  H01L27/10861 ,  H01L29/66181 ,  Y10S257/906 ,  Y10S257/908

摘要： In a DRAM-logic embedded integrated circuit in which a DRAM including trench capacitors of the deep trench structure and a logic circuit are mixedly formed in a semiconductor substrate, a plurality of capacitors of the deep trench structure are provided in the logic circuit portion. The plurality of capacitors are connected in parallel by wiring portions, whereby a plurality of capacitor blocks are formed. Between the respective capacitor blocks, there are provided fuse elements which selectively connect the respective wiring portions to each other or selectively separate them from each other to thereby vary the capacitance value of the capacitance blocks. These fuse elements are selectively cut off depending on the capacitance value of the capacitors required in view of the circuit design.

摘要翻译： 在其中包括深沟槽结构的沟槽电容器的DRAM和逻辑电路混合形成在半导体衬底中的DRAM逻辑嵌入式集成电路中，在逻辑电路部分中设置有多个深沟槽结构的电容器。 多个电容器通过布线部并联连接，从而形成多个电容器块。 在相应的电容器块之间，提供了熔丝元件，其选择性地将各个布线部分彼此连接或者将它们彼此分离，从而改变电容块的电容值。 根据电路设计所需的电容器的电容值，这些熔丝元件被选择性地切断。

公开(公告)号：US08644059B2

公开(公告)日：2014-02-04

申请号：US13419258

申请日：2012-03-13

申请人： Yoshiaki Asao

发明人： Yoshiaki Asao

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C11/161 ,  G11C11/1659

摘要： A memory includes MTJ elements. Active areas are separated to correspond to cell transistors, respectively, and extend in a first direction substantially orthogonal to an extending direction of gates of the cell transistors. The active areas are arranged in the first direction and constitute a plurality of active area columns. Two active area columns adjacent in a second direction are arranged to be half-pitch staggered in the first direction. As viewed from above surfaces of the active areas, each MTJ element is arranged to overlap with one end of each of the active areas. The first and second wirings extend while being folded back in a direction inclined with respect to the first and second directions in order to overlap with the MTJ elements alternately in the adjacent active area columns.

摘要翻译： 内存包括MTJ元素。 有源区域分别对应于单元晶体管，并且在与单元晶体管的栅极的延伸方向基本正交的第一方向上延伸。 有源区域沿第一方向布置并且构成多个有效区域列。 在第二方向相邻的两个有效区列被布置为在第一方向上半间距交错。 从有源区域的上表面观察，每个MTJ元件被布置成与每个有源区域的一端重叠。 第一和第二布线在相对于第一和第二方向倾斜的方向被折回的同时延伸，以便在相邻的有效区域列中交替地与MTJ元件重叠。

公开(公告)号：US08604569B2

公开(公告)日：2013-12-10

申请号：US12243250

申请日：2008-10-01

申请人： Keiji Hosotani ,  Yoshiaki Asao

发明人： Keiji Hosotani ,  Yoshiaki Asao

IPC分类号： H01L29/82

CPC分类号： H01L43/10 ,  B82Y25/00 ,  G11C11/161 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3263 ,  H01F10/3286 ,  H01L27/228 ,  H01L43/08

摘要： A magnetoresistive element includes a first electrode layer, a first fixed layer provided on the first electrode layer and having a fixed magnetization direction, a first intermediate layer provided on the first fixed layer and made of a metal oxide, a free layer provided on the first intermediate layer and having a variable magnetization direction, and a second electrode layer provided on the free layer. At least one of the first electrode layer and the second electrode layer contains a conductive metal oxide.

摘要翻译： 磁阻元件包括第一电极层，设置在第一电极层上并具有固定的磁化方向的第一固定层，设置在第一固定层上并由金属氧化物制成的第一中间层，设置在第一电极层上的自由层 中间层并且具有可变的磁化方向，以及设置在自由层上的第二电极层。 第一电极层和第二电极层中的至少一个包含导电金属氧化物。

公开(公告)号：US07781803B2

公开(公告)日：2010-08-24

申请号：US12339814

申请日：2008-12-19

申请人： Jun Nishimura ,  Yoshiaki Asao

发明人： Jun Nishimura ,  Yoshiaki Asao

IPC分类号： H01L27/11

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A semiconductor memory device comprising: a support substrate; an insulating film formed on the support substrate; a semiconductor film formed on the insulating film; a gate insulating film formed on the semiconductor film; a gate electrode film formed on the gate insulating film; and a source region and a drain region formed in the semiconductor film so as to sandwich the gate insulating film in a gate length direction, the source and drain regions contacting the insulating film at the bottom surface, and the semiconductor memory device storing data corresponding to the amount of charges accumulated in the semiconductor film surrounded by the insulating film, the gate insulating film, and the source and drain regions and electrically floated, wherein a border length between the source region and the gate insulating film contiguous to each other is different from a border length between the drain region and the gate insulating film to each other.

摘要翻译： 一种半导体存储器件，包括：支撑衬底; 形成在所述支撑基板上的绝缘膜; 形成在绝缘膜上的半导体膜; 形成在半导体膜上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极膜; 以及形成在所述半导体膜中的源极区域和漏极区域，以便在栅极长度方向夹着所述栅极绝缘膜，所述源极和漏极区域在所述底面处与所述绝缘膜接触，并且所述半导体存储器件存储对应于 在由绝缘膜，栅极绝缘膜以及源极和漏极区域包围的半导体膜中积累的电荷量被电浮动，其中源极区域和栅极绝缘膜彼此相邻的边界长度不同于 漏极区域和栅极绝缘膜之间的边界长度彼此。