公开(公告)号：US07893499B2

公开(公告)日：2011-02-22

申请号：US12417810

申请日：2009-04-03

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20100252882A1

公开(公告)日：2010-10-07

申请号：US12417810

申请日：2009-04-03

申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

公开(公告)号：US20100241413A1

公开(公告)日：2010-09-23

申请号：US12406423

申请日：2009-03-18

申请人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

发明人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.

摘要翻译： 提供了一种其上实施有用于对具有漂移区域的LDMOS晶体管进行建模的计算机程序产品的处理器。 产生其主体与其源极耦合的CMOS晶体管的特性，并且产生电阻器的特性，其中电阻器耦合到CMOS晶体管的漏极。 然后考虑到冲击电离，计算漂移区域中电子的冲击电离电流对漂移区中空穴的电离电流。

公开(公告)号：US07602019B2

公开(公告)日：2009-10-13

申请号：US11408692

申请日：2006-04-20

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/72

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/66659 ,  H03K19/00384

摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

摘要翻译： 晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。 晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。 在第一半导体区域和第二半导体区域之间存在界面。 晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。 还描述了一种混合技术电路。

公开(公告)号：US20090068804A1

公开(公告)日：2009-03-12

申请号：US12273850

申请日：2008-11-19

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和 晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

公开(公告)号：US07498652B2

公开(公告)日：2009-03-03

申请号：US10832009

申请日：2004-04-26

申请人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

发明人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

IPC分类号： H01L29/93

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

公开(公告)号：US07468537B2

公开(公告)日：2008-12-23

申请号：US11012469

申请日：2004-12-15

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和 晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

公开(公告)号：US07427795B2

公开(公告)日：2008-09-23

申请号：US10880907

申请日：2004-06-30

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

摘要翻译： 描述了漏极扩散MOS晶体管（T 1，T 2）和半导体器件（102）及其制造方法（202），其中在形成外延硅之前形成p埋层（130） 106），并且在外延硅层（106）中形成漏极扩展MOS晶体管（T 1，T 2）。 p埋层（130）可以形成在用于高侧驱动晶体管（T 2）应用的衬底（104）中的n掩埋层（120）上方，其中p埋层（130）在 漏极扩展MOS晶体管（T 2）和n掩埋层（120），以抑制源极（154）和漏极（156）之间的截止状态击穿。

公开(公告)号：US20070246773A1

公开(公告)日：2007-10-25

申请号：US11408692

申请日：2006-04-20

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/66659 ,  H03K19/00384

摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

摘要翻译： 晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。 晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。 在第一半导体区域和第二半导体区域之间存在界面。 晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。 还描述了一种混合技术电路。

公开(公告)号：US07235451B2

公开(公告)日：2007-06-26

申请号：US10378402

申请日：2003-03-03

申请人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

发明人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/7835

摘要： Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

摘要翻译： 公开了半导体器件及其制造方法，其中漏极扩展MOS晶体管包括靠近晶体管栅极的一端的自对准浮置区，并掺杂有第一类型掺杂剂以减少通道热载流子劣化，以及相反地 掺杂的第一源极/漏极在半导体本体中与栅极结构的第一端横向间隔开。 该器件还可以包括掺杂到比浮置区域更低的浓度的复现区域，以便于改进的击穿电压性能。 公开了一种在半导体器件中制造漏极扩展MOS晶体管的方法，包括：向半导体本体中的浮置区域提供第一掺杂物，所述浮置区域与栅极结构的第一端自对准，并提供第二掺杂剂到源极 /半导体主体的漏极，其中第一和第二掺杂剂是不同的。