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    Methods of fabricating high voltage devices
    1.
    发明授权
    Methods of fabricating high voltage devices 有权
    制造高压器件的方法

    公开(公告)号：US07208364B2

    公开(公告)日：2007-04-24

    申请号：US11154431

    申请日：2005-06-16

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James R. Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James R. Todd

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

    摘要翻译： 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

    SEMICONDUCTOR WELL IMPLANTED THROUGH PARTIALLY BLOCKING MATERIAL PATTERN
    3.
    发明申请
    SEMICONDUCTOR WELL IMPLANTED THROUGH PARTIALLY BLOCKING MATERIAL PATTERN 审中-公开
    半导体器件通过部分阻塞材料图案进行了良好的嵌入

    公开(公告)号：US20100035421A1

    公开(公告)日：2010-02-11

    申请号：US12536778

    申请日：2009-08-06

    申请人： Marie Denison ,  Shanjen Pan

    发明人： Marie Denison ,  Shanjen Pan

    IPC分类号： H01L21/265

    CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/1066 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66893 ,  H01L29/7394 ,  H01L29/7835 ,  H01L29/8086 ,  H01L29/8605

    摘要： A method for forming a partially blocking layer for an ion implantation process, which may be varied across the IC to form regions with different dopant concentrations, and regions with varying dopant concentrations in each contiguously implanted region, is disclosed. One or more temporary and/or permanent layers may form the partially blocking layer, including a combination of different materials such as polysilicon, silicon dioxide, silicon nitride, and photoresist. The partially blocking layer may be a uniform continuous sheet which transmits a uniform fraction of dopants, or a reticulated screen which transmits dopants through multiple open areas. Several partially blocking layers, each absorbing a different fraction of implanted dopants, may be formed on an IC to produce instances of a component with different performance parameters such as operation voltage, sheet resistance or gain.

    摘要翻译： 公开了一种用于形成用于离子注入工艺的部分阻挡层的方法，其可以在IC两端形成，以形成具有不同掺杂剂浓度的区域，以及在每个连续注入区域中具有变化的掺杂剂浓度的区域。 一个或多个临时和/或永久层可以形成部分阻挡层，包括不同材料的组合，例如多晶硅，二氧化硅，氮化硅和光致抗蚀剂。 部分阻挡层可以是均匀连续的片材，其传输均匀分数的掺杂剂，或通过多个开放区域传输掺杂剂的网状筛网。 可以在IC上形成吸收不同部分的注入掺杂剂的几个部分阻挡层，以产生具有不同性能参数（例如操作电压，薄层电阻或增益）的部件的实例。

    Drain extended PMOS transistor with increased breakdown voltage
    4.
    发明申请
    Drain extended PMOS transistor with increased breakdown voltage 有权
    以增加的击穿电压漏极扩展PMOS晶体管

    公开(公告)号：US20060170056A1

    公开(公告)日：2006-08-03

    申请号：US11047418

    申请日：2005-01-31

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

    摘要翻译： 提供了包括漏极延伸PMOS晶体管（CT1a）的半导体器件（102），以及制造方法（202）。 在形成PMOS晶体管时，晶体管的漏极（124）形成在p型上部外延层（106）的区域（125）上，其中p型上部外延层（106）的区域（125） ）夹在形成在p型上部外延层（106）内的左P-WELL区域（130a）和右P-WELL区域（130b）之间。 p型上部外延层（106）形成在其上形成有n埋层（108）的半导体本体（104）上。 这种布置用于增加漏极延伸PMOS晶体管的击穿电压（BVdss）。

    Methods for fabricating low CHC degradation mosfet transistors
    6.
    发明授权
    Methods for fabricating low CHC degradation mosfet transistors 有权
    制造低CHC降解mosfet晶体管的方法

    公开(公告)号：US06803282B2

    公开(公告)日：2004-10-12

    申请号：US10020034

    申请日：2001-12-07

    申请人： Jozef D. Mitros ,  James R. Todd ,  Shanjen Pan ,  Tsutomu Kubota

    发明人： Jozef D. Mitros ,  James R. Todd ,  Shanjen Pan ,  Tsutomu Kubota

    IPC分类号： H01L218234

    CPC分类号： H01L21/823462 ,  H01L21/823418

    摘要： Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

    摘要翻译： 公开了用于在半导体器件中制造厚和薄栅极氧化物晶体管的方法和装置，其中使用阈值电压调整注入形成用于厚栅极氧化物晶体管的轻掺杂源极/漏极区域，以及用于薄的栅极氧化物薄层的轻掺杂源极/漏极区域 使用LDD植入物形成栅极氧化物晶体管。 使用阈值电压注入形成厚栅极氧化物晶体管的轻掺杂源极/漏极区域，与薄栅极氧化物晶体管相比允许较低的掺杂剂浓度，而不需要对不同栅极氧化物厚度的晶体管进行单独的LDD注入处理。

    Drain extended MOS devices with self-aligned floating region and fabrication methods therefor
    8.
    发明授权
    Drain extended MOS devices with self-aligned floating region and fabrication methods therefor 有权
    排水扩展MOS器件具有自对准浮动区域及其制造方法

    公开(公告)号：US07235451B2

    公开(公告)日：2007-06-26

    申请号：US10378402

    申请日：2003-03-03

    申请人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

    发明人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66659 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/7835

    摘要： Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

    摘要翻译： 公开了半导体器件及其制造方法，其中漏极扩展MOS晶体管包括靠近晶体管栅极的一端的自对准浮置区，并掺杂有第一类型掺杂剂以减少通道热载流子劣化，以及相反地 掺杂的第一源极/漏极在半导体本体中与栅极结构的第一端横向间隔开。 该器件还可以包括掺杂到比浮置区域更低的浓度的复现区域，以便于改进的击穿电压性能。 公开了一种在半导体器件中制造漏极扩展MOS晶体管的方法，包括：向半导体本体中的浮置区域提供第一掺杂物，所述浮置区域与栅极结构的第一端自对准，并提供第二掺杂剂到源极 /半导体主体的漏极，其中第一和第二掺杂剂是不同的。

    Reduction of channel hot carrier effects in transistor devices
    9.
    发明授权
    Reduction of channel hot carrier effects in transistor devices 有权

    公开(公告)号：US07135373B2

    公开(公告)日：2006-11-14

    申请号：US10670434

    申请日：2003-09-23

    申请人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

    发明人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

    Method for manufacturing a metal oxide transistor having reduced 1/f noise
    10.
    发明申请
    Method for manufacturing a metal oxide transistor having reduced 1/f noise 有权
    制造具有降低的1 / f噪声的金属氧化物晶体管的方法

    公开(公告)号：US20050136579A1

    公开(公告)日：2005-06-23

    申请号：US10744549

    申请日：2003-12-22

    申请人： Pinghai Hao ,  Larry Anderson ,  Fan Chi Hou ,  Xiaoju Wu ,  Yvonne Patton ,  Shanjen Pan ,  Zafar Imam

    发明人： Pinghai Hao ,  Larry Anderson ,  Fan Chi Hou ,  Xiaoju Wu ,  Yvonne Patton ,  Shanjen Pan ,  Zafar Imam

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L21/28176 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/823857 ,  H01L29/7833

    摘要： The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.

    摘要翻译： 本发明在一个实施例中提供一种降低金属氧化物半导体（MOS）器件（100）中的1 / f噪声的方法。 该方法包括在硅衬底（105）上形成氧化物层（110）并在氧化物层（110）上沉积多晶硅层（115）。 该方法还包括以至少约4×10 14原子/ cm 2的注入剂量将氟掺杂剂（130）注入到多晶硅层（115）中。 多晶硅层（115）被热退火，使得氟掺杂剂（130）的一部分扩散到氧化物层（110）中，从而降低MOS器件（100）的1 / f噪声。 提供通过上述方法制造的MOS器件（300）和包括上述方法的集成电路（500）的制造方法的其它实施例。