公开(公告)号：US06819619B2

公开(公告)日：2004-11-16

申请号：US10356560

申请日：2003-02-03

申请人： Fukashi Morishita ,  Hiroshi Kato

发明人： Fukashi Morishita ,  Hiroshi Kato

IPC分类号： G11C514

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C5/147 ,  G11C2207/104

摘要： A semiconductor memory device includes a memory cell array, a data bus, a reference voltage generating circuit, a voltage down converter, a VPP generating circuit, a circuit group, and a test circuit. The reference voltage generating circuit, voltage down converter, and VPP generating circuit include thick film transistors having a gate oxide film thickness suitable to a power supply voltage of 3.3 V. Circuits included in the circuit group include thin film transistors having a gate oxide film thickness suitable to a power supply voltage of 1.5 V. The reference voltage generating circuit, voltage down converter, and VPP generating circuit including the thick film transistors are arranged to form units corresponding to the position of the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，数据总线，参考电压产生电路，降压转换器，VPP生成电路，电路组和测试电路。 参考电压产生电路，降压转换器和VPP产生电路包括具有适合于3.3V的电源电压的栅极氧化膜厚度的厚膜晶体管。电路组中包括的电路包括具有栅氧化物膜厚度 适合于1.5V的电源电压。包括厚膜晶体管的参考电压产生电路，降压转换器和VPP产生电路被布置成形成与存储单元阵列的位置对应的单元。

公开(公告)号：US06434078B1

公开(公告)日：2002-08-13

申请号：US09503719

申请日：2000-02-14

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G11C514

CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C29/12

摘要： In a voltage down converter, an internal power supply potential can be made equal to an external power supply potential by rendering an output driving transistor included in differential amplifiers conductive in accordance with an activation of a burn-in mode detection signal. The differential amplifiers include a comparison circuit having an output changed to an inactive state in response to the burn-in mode detection signal and a transistor setting a level of a gate voltage of the drive transistor to a fixed level.

公开(公告)号：US06385117B1

公开(公告)日：2002-05-07

申请号：US09843691

申请日：2001-04-30

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G11C800

摘要： A voltage generating circuit of the present invention includes a charge pump regulator and a voltage converting circuit. Charge pump regulator receives Ext.Vcc and a ground voltage as inputs and outputs a negative voltage Vbb1. Charge pump regulator receives Int.Vcc and negative voltage Vbb1 as inputs and outputs negative voltage Vbb2(

公开(公告)号：US06323689B1

公开(公告)日：2001-11-27

申请号：US09088703

申请日：1998-06-02

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： H01L2500

CPC分类号： H01L27/0251

摘要： The interlayer capacitance between a first metal interconnection through which a control signal is transmitted to the gate of a drive transistor and respective power supply interconnections through which a power supply potential and a ground potential is supplied is sufficiently smaller than the interlayer capacitance between an interconnection connecting a drain of the drive transistor and the first metal interconnection. The power supply interconnection is not coupled to a signal input to the gate of the drive transistor.

摘要翻译： 通过其将控制信号传输到驱动晶体管的栅极的第一金属互连和供电电位和接地电位之间的相互供电互连的层间电容充分小于互连连接 驱动晶体管的漏极和第一金属互连。 电源互连不耦合到输入到驱动晶体管的栅极的信号。

公开(公告)号：US5877978A

公开(公告)日：1999-03-02

申请号：US710215

申请日：1996-09-13

申请人： Fukashi Morishita ,  Shigeki Tomishima ,  Kazutani Arimoto

发明人： Fukashi Morishita ,  Shigeki Tomishima ,  Kazutani Arimoto

IPC分类号： H01L21/76 ,  G11C11/401 ,  G11C11/404 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C11/4074 ,  H01L29/7841

摘要： In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.

公开(公告)号：US5867418A

公开(公告)日：1999-02-02

申请号：US957375

申请日：1997-10-24

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108 ,  G11C7/02

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

公开(公告)号：US5757175A

公开(公告)日：1998-05-26

申请号：US782036

申请日：1997-01-13

申请人： Fukashi Morishita ,  Masaki Tsukude ,  Tsukasa Ooishi ,  Kyoji Yamasaki

发明人： Fukashi Morishita ,  Masaki Tsukude ,  Tsukasa Ooishi ,  Kyoji Yamasaki

IPC分类号： G05F3/26 ,  G05F3/24 ,  G11C11/407 ,  H03F3/343 ,  G05F3/16

CPC分类号： G05F3/242

摘要： A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.

摘要翻译： 在第一p沟道MOS晶体管和接地节点之间提供电流源，并且电流/电压转换元件与接地节点和具有足够大的电导系数的第二p沟道MOS晶体管之间的电流源隔离地提供。 的第一MOS晶体管。 第二MOS晶体管通过电阻元件连接到外部电源节点。 由电流/电压转换元件产生的电压由电压/电流转换部分转换成电流。 因此，提供不受振动和死锁现象以及小外部电源电压依赖性的恒定电流。

公开(公告)号：US07656736B2

公开(公告)日：2010-02-02

申请号：US11717717

申请日：2007-03-14

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US20090003091A1

公开(公告)日：2009-01-01

申请号：US12201024

申请日：2008-08-29

申请人： Kenji Yoshinaga ,  Fukashi Morishita

发明人： Kenji Yoshinaga ,  Fukashi Morishita

IPC分类号： G11C5/14 ,  G11C7/10

CPC分类号： G11C5/147

摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。

公开(公告)号：US07397315B2

公开(公告)日：2008-07-08

申请号：US11311301

申请日：2005-12-20

申请人： Masanobu Kishida ,  Fukashi Morishita

发明人： Masanobu Kishida ,  Fukashi Morishita

IPC分类号： H03B27/00

CPC分类号： H03K3/0315 ,  H03K17/063

摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

摘要翻译： 本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。 限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流 所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器 并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。