公开(公告)号：US5757175A

公开(公告)日：1998-05-26

申请号：US782036

申请日：1997-01-13

申请人： Fukashi Morishita ,  Masaki Tsukude ,  Tsukasa Ooishi ,  Kyoji Yamasaki

发明人： Fukashi Morishita ,  Masaki Tsukude ,  Tsukasa Ooishi ,  Kyoji Yamasaki

IPC分类号： G05F3/26 ,  G05F3/24 ,  G11C11/407 ,  H03F3/343 ,  G05F3/16

CPC分类号： G05F3/242

摘要： A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.

摘要翻译： 在第一p沟道MOS晶体管和接地节点之间提供电流源，并且电流/电压转换元件与接地节点和具有足够大的电导系数的第二p沟道MOS晶体管之间的电流源隔离地提供。 的第一MOS晶体管。 第二MOS晶体管通过电阻元件连接到外部电源节点。 由电流/电压转换元件产生的电压由电压/电流转换部分转换成电流。 因此，提供不受振动和死锁现象以及小外部电源电压依赖性的恒定电流。

公开(公告)号：US5917765A

公开(公告)日：1999-06-29

申请号：US951591

申请日：1997-10-16

申请人： Fukashi Morishita ,  Masaki Tsukude

发明人： Fukashi Morishita ,  Masaki Tsukude

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  G11C13/00

CPC分类号： G11C29/50008 ,  G11C29/028 ,  G11C29/50 ,  G11C5/147 ,  G11C11/401 ,  G11C2029/5004

摘要： A semiconductor integrated circuit device realizing high speed operation and low current consumption and ensure reliability evaluation is provided. Reference voltage generating circuits for generating reference voltages of mutually different voltage levels are provided for power supply pads respectively, and voltage down converters for down converting power supply voltages of corresponding external power supply pads to corresponding reference voltage levels and transmitting the lowered voltages to corresponding internal power supply lines are provided corresponding to respective reference voltage generating circuits. Further, a switching transistor is provided at an output node of the reference voltage generating circuit which is rendered conductive at a stress acceleration mode for connecting the corresponding external power supply pad to the output node of the corresponding reference voltage generating circuit.

摘要翻译： 提供实现高速运行和低电流消耗并确保可靠性评估的半导体集成电路装置。 提供用于产生相互不同电压电平的参考电压的参考电压产生电路，以及用于将相应的外部电源焊盘的电源电压下变换为相应的参考电压电平的降压转换器，并将降低的电压传输到相应的内部 对应于各个参考电压产生电路提供电源线。 此外，开关晶体管设置在基准电压产生电路的输出节点处，其以应力加速模式导通，用于将相应的外部电源焊盘连接到相应的参考电压产生电路的输出节点。

公开(公告)号：US5909046A

公开(公告)日：1999-06-01

申请号：US965618

申请日：1997-11-06

申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

公开(公告)号：US5694364A

公开(公告)日：1997-12-02

申请号：US779186

申请日：1997-01-06

申请人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/147

摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.

摘要翻译： 在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器 降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。 这允许快速操作和降低功耗。 在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。 因此，第一和第二内部电源电压供给线直接接收外部电源电压。 这允许有效的老化测试。 在老化测试中，第一和第二降压转换器失效。

公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5894440A

公开(公告)日：1999-04-13

申请号：US189276

申请日：1994-01-31

申请人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

发明人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC分类号： G11C7/06 ,  G11C7/1006 ,  G11C7/1039

摘要： Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

摘要翻译： 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。

公开(公告)号：US5267214A

公开(公告)日：1993-11-30

申请号：US616264

申请日：1990-11-20

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/34

CPC分类号： G11C11/4091 ,  G11C11/4076

摘要： A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

摘要翻译： 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。

公开(公告)号：US4977542A

公开(公告)日：1990-12-11

申请号：US400898

申请日：1989-08-30

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14

CPC分类号： G11C7/14 ,  G11C7/18 ,  G11C8/14

摘要： An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

摘要翻译： 一种用于在包括扭转位线的存储器结构中提供字线和位线之间的电容耦合补偿的装置。 保持在预定电位的两个虚拟字线形成在一对位线的扭转部分。 在虚拟字线和位线的相应扭转部分设置虚拟单元。 在与位线相交的方向上形成多个字线，并且根据位线对的扭绞部分的位置将字线分成四个字线组。 当选择任意字线时，与所选字线所属的字线组对应的至少一个虚拟字线的电位降低。 因此，通过降低至少一个虚拟字线的电位来补偿由字线的选择引起的位线的电位的上升，使得可以减少读取中的误差。 特殊的单元层布置简化了虚拟单元补偿与电容耦合的扭转位线平衡组合的集成密度的增加。

公开(公告)号：US5982678A

公开(公告)日：1999-11-09

申请号：US882758

申请日：1997-06-26

申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC分类号： G11C29/806 ,  G11C29/781 ,  G11C8/10

摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

公开(公告)号：US5022007A

公开(公告)日：1991-06-04

申请号：US506616

申请日：1990-04-10

申请人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/34 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/34

摘要： A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.

摘要翻译： 一种用于半导体集成电路存储器的测试信号发生器，其中当传输晶体管（20,21,14,15）导通时，测试数据线从I / O线对（11,12）提供到 寄存器（10）并存储在其中。 当传送（67）导通时，写入寄存器的测试数据列以相同的模式写入存储单元（22）的列中，并且当传输晶体管（16,17）导通时，测试数据 写入寄存器的列被反相，并且写入存储单元列中，存储单元列中的数据被字线（13）读出并由读出放大器（5）放大，使得数据和测试 存储在寄存器中的数据由重合检测电路8进行比较，以检测其是否一致。