公开(公告)号：US6122729A

公开(公告)日：2000-09-19

申请号：US929413

申请日：1997-09-15

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/42

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/3816

Abstract: A prefetch/predecode unit includes one or more prefetch buffers which are configured to store prefetched sets of instruction bytes and corresponding predecode data. Additionally, each prefetch buffer is configured to store a predecode byte pointer. The predecode byte pointer indicates the byte within the corresponding prefetched set of instruction bytes at which predecoding is to be initiated. Predecoding may be resumed within a given prefetch buffer (at the byte indicated by the predecode byte pointer) if predecoding thereof is interrupted to predecode a different set of instruction bytes (e.g. a set of instruction bytes fetched from the instruction cache).

Abstract translation: 预取/预解码单元包括一个或多个预取缓冲器，其被配置为存储预取指令字节集合和相应的预代码数据。 另外，每个预取缓冲器被配置为存储预解码字节指针。 预代码字节指针指示在要启动预解码的相应预取指令字节集合内的字节。 如果其预解码被中断以对一组不同的指令字节（例如，从指令高速缓存取出的一组指令字节）进行预解码，则可以在给定的预取缓冲器（在由预解码字节指针指示的字节）下恢复预编码。

公开(公告)号：US6112018A

公开(公告)日：2000-08-29

申请号：US992804

申请日：1997-12-18

Applicant: Thang M. Tran ,  Derrick R. Meyer

Inventor： Thang M. Tran ,  Derrick R. Meyer

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/3816 ,  G06F9/30134 ,  G06F9/30152 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3842

Abstract: A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands. Finally, the functional pipelines execute the instructions.

Abstract translation: 公开了一种能够使用中央窗口和寄存器映射在单个时钟周期中执行多个指令的浮点单元。 浮点单元包括：多个翻译单元，未来文件，中央窗口，多个功能单元，结果队列和多个物理寄存器。 浮点单元接收推测指令，对它们进行解码，然后将其存储在中央窗口中。 在解码过程中，每个指令产生堆栈值的推测顶点。 堆栈顶部相对操作数使用寄存器映射计算到物理寄存器。 在解码期间执行寄存器堆栈交换操作。 然后将指令存储在中央窗口中，其中选择要发布到每个功能管道的最早存储的指令并发出它们。 转换单位将指令的操作数转换为内部格式，归一化单元检测和归一化任何反常操作数。 最后，功能管线执行指令。

公开(公告)号：US6101595A

公开(公告)日：2000-08-08

申请号：US246270

申请日：1999-02-08

Applicant: James K. Pickett ,  Thang M. Tran

Inventor： James K. Pickett ,  Thang M. Tran

IPC: G06F9/38 ,  G06F12/08 ,  G06F15/00

CPC classification number: G06F9/3806 ,  G06F12/0864 ,  G06F9/3814 ,  G06F2212/6082

Abstract: An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a first group of contiguous instruction bytes within the instruction cache, as well as a corresponding branch prediction block. The branch prediction block is stored in a branch prediction storage, and includes a predicted sequential way value. The control unit is further configured to convey a second index and a second way to the instruction cache in a second clock cycle succeeding the first clock cycle. This second index and second way select a second group of contiguous instruction bytes from the instruction cache. The second way is selected to be the predicted sequential way value stored in the branch prediction block corresponding to the first group of contiguous instruction bytes in response to a branch prediction algorithm employed by the control unit predicting a sequential execution path. Advantageously, a set associative instruction cache utilizing this method of way prediction may operate at higher frequencies (i.e., lower clock cycles) than if tag comparison were used to select the correct way.

Abstract translation: 采用顺序方式预测的指令提取单元。 指令提取单元包括控制单元，其被配置为在第一时钟周期中将第一索引和第一路径传送到指令高速缓存。 第一索引和第一方式选择指令高速缓存内的第一组连续指令字节，以及相应的分支预测块。 分支预测块存储在分支预测存储器中，并且包括预测的顺序路径值。 控制单元还被配置为在第一时钟周期之后的第二时钟周期中将第二索引和第二路径传送到指令高速缓存。 该第二索引和第二方式从指令高速缓存中选择第二组连续的指令字节。 响应于预测顺序执行路径的控制单元使用的分支预测算法，第二种方式被选择为存储在与第一组连续指令字节对应的分支预测块中的预测顺序方式值。 有利地，使用这种方式预测方法的集合关联指令高速缓存可以比使用标签比较来选择正确的方式更高的频率（即，较低的时钟周期）操作。

公开(公告)号：US6012125A

公开(公告)日：2000-01-04

申请号：US879588

申请日：1997-06-20

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/28 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F9/382 ,  G06F12/0875 ,  G06F9/28 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3808

Abstract: A decoded instruction cache which stores both directly executable and microcode instructions for concurrent dispatch to a plurality of issue positions. An instruction address required by a superscalar microprocessor is first presented to the decoded instruction cache. If the address is not present in the decoded instruction cache, the instruction bytes are retrieved either from an instruction cache or main memory. In either case, a group of instruction bytes are conveyed to an early decode unit, which performs partial decoding on the instructions therein. These partially decoded instructions are conveyed to the decoded instruction cache for storage. If the first instruction conveyed from the group of instruction bytes is a directly executable instruction, the partially decoded information corresponding to the first instruction is stored in a cache line selected according to the opcode of the first instruction. Directly executable instructions subsequent to the first instruction in the group of instruction bytes may be stored in succeeding locations in the same cache line. If the first instruction is a microcode instruction, operand information provided by the early decode unit is stored to one or more cache lines including directly executable instructions which, when executed, effectuate the operation of that microcode instruction. When a read is performed on a valid line in the decoded instruction cache, partially decoded instructions already aligned for dispatch are conveyed to a plurality of issue positions.

Abstract translation: 解码指令高速缓存，其存储用于并行发送到多个发行位置的直接可执行和微码指令。 超标量微处理器所需的指令地址首先被提供给解码的指令高速缓存。 如果解码指令高速缓存中不存在该地址，则从指令高速缓存或主存储器检索指令字节。 在任一情况下，一组指令字节被传送到早期解码单元，其对其中的指令执行部分解码。 这些部分解码的指令被传送到解码的指令高速缓存用于存储。 如果从指令字节组传送的第一指令是直接执行指令，则与第一指令对应的部分解码信息存储在根据第一指令的操作码选择的高速缓存行中。 指令字节组中的第一指令之后的直接可执行指令可以存储在同一高速缓存行中的后续位置。 如果第一指令是微码指令，则由早期解码单元提供的操作数信息被存储到包括直接可执行指令的一个或多个高速缓存行，该指令在被执行时执行该微代码指令的操作。 当在解码的指令高速缓存中的有效行执行读取时，已经对准发送的部分解码的指令被传送到多个发行位置。

公开(公告)号：US5968163A

公开(公告)日：1999-10-19

申请号：US814629

申请日：1997-03-10

Applicant: Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

Inventor： Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

IPC: G06F9/28 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/382 ,  G06F9/28 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/3816 ,  G06F9/3867

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

Abstract translation: 公开了一种用于超标量微处理器的指令扫描单元。 指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。 开始字节信息和结束字节信息的处理是独立并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。 另外，指示扫描单元是可扩展的。 可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。 此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。 此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

公开(公告)号：US5961638A

公开(公告)日：1999-10-05

申请号：US67990

申请日：1998-04-29

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3844

Abstract: A branch prediction apparatus is provided which stores multiple branch selectors corresponding to instruction bytes within a cache line of instructions or portion thereof. The branch selectors identify a branch prediction to be selected if the corresponding instruction byte is the byte indicated by the offset of the fetch address used to fetch the cache line. Instead of comparing pointers to the branch instructions with the offset of the fetch address, the branch prediction is selected simply by decoding the offset of the fetch address and choosing the corresponding branch selector. The branch prediction apparatus may operate at a higher frequencies (i.e. lower clock cycles) than if the pointers to the branch instruction and the fetch address were compared (a greater than or less than comparison). The branch selectors directly determine which branch prediction is appropriate according to the instructions being fetched, thereby decreasing the amount of logic employed to select the branch prediction.

Abstract translation: 提供了一种分支预测装置，其存储与指令或其部分的高速缓存行中的指令字节对应的多个分支选择器。 如果相应的指令字节是由用于获取高速缓存线的提取地址的偏移指示的字节，则分支选择器识别要选择的分支预测。 代替将指针与获取地址偏移量的分支指令进行比较，通过解码获取地址的偏移并选择相应的分支选择器简单地选择分支预测。 分支预测装置可以比比较分支指令和获取地址的指针（大于或小于比较）更高的频率（即较低的时钟周期）操作。 分支选择器根据所取指令直接确定哪个分支预测是适当的，从而减少用于选择分支预测的逻辑量。

公开(公告)号：US5901302A

公开(公告)日：1999-05-04

申请号：US690384

申请日：1996-07-26

Applicant: David B. Witt ,  Thang M. Tran

Inventor： David B. Witt ,  Thang M. Tran

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/12

CPC classification number: G06F9/52 ,  G06F12/126 ,  G06F9/30036 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

Abstract: A microprocessor employing a reorder buffer is configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. In one embodiment, the reorder buffer allocates a line of storage sufficient to store instruction results corresponding to a maximum number of concurrently dispatchable instructions regardless of the number actually dispatched. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases.

Abstract translation: 采用重排序缓冲器的微处理器配置有固定的对称发布位置。 问题位置的对称性质可能会增加由微处理器同时调度和执行的指令的平均数量。 在一个实施例中，重新排序缓冲器分配足够的存储线，以便存储对应于最大数量的可同时分发的指令的指令结果，而不管实际发送的数目如何。 随着并发调度指令的平均数量的增加，行中未使用位置的平均数量减少。

公开(公告)号：US5898851A

公开(公告)日：1999-04-27

申请号：US873115

申请日：1997-06-11

Applicant: Rammohan Narayan ,  Thang M. Tran

Inventor： Rammohan Narayan ,  Thang M. Tran

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/318 ,  G06F9/40

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/3816

Abstract: A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and two ROP bits. The ROP bits indicate a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified. Accordingly, relatively fast multiplexing may be attained, and high performance may be accommodated.

Abstract translation: 提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。 预解码单元被配置为为每个指令字节生成多个预解码位。 与每个指令字节相关联的多个预解码位包括结束位和两个ROP位。 ROP位指示实现该指令所需的微指令数。 多个预解码比特统称为预解码标签。 指令对齐单元然后使用预解码标签来识别微指令。 指令对准单元将微指令同时分配到在超标量微处理器内形成固定发行位置的多个解码单元。 由于指令对准单元识别微指令，简化了从指令对准单元到解码器的指令的复用。 因此，可以实现相对快速的复用，并且可以适应高性能。

公开(公告)号：US5887152A

公开(公告)日：1999-03-23

申请号：US420737

申请日：1995-04-12

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/38

CPC classification number: G06F9/3812 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857

Abstract: A superscalar microprocessor is provided having a load/store unit which receives a pair of pointers identifying the oldest outstanding instructions which are not in condition for retirement. The load/store unit compares these pointers with the reorder buffer tags of load instructions that miss the data cache and store instructions. A match must be found before the associated instruction accesses the data cache and the main memory system. The pointer-compare mechanism provides an ordering mechanism for load instructions that miss the data cache and store instructions.

Abstract translation: 提供了一种超标量微处理器，其具有负载/存储单元，该单元接收一对指示符，用于识别不符合退休条件的最早的未完成指令。 加载/存储单元将这些指针与错过数据高速缓存和存储指令的加载指令的重新排序缓冲区标记进行比较。 必须在关联指令访问数据高速缓存和主存储器系统之前找到匹配项。 指针比较机制为缺少数据高速缓存和存储指令的加载指令提供了排序机制。

公开(公告)号：US5878244A

公开(公告)日：1999-03-02

申请号：US690385

申请日：1996-07-26

Applicant: David B. Witt ,  Thang M. Tran

Inventor： David B. Witt ,  Thang M. Tran

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/12

CPC classification number: G06F9/3836 ,  G06F12/126 ,  G06F9/30036 ,  G06F9/382 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/52

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instructions results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. The line of storage remains allocated until each instruction within the line is ready to retire, and then the line is deallocated as the one or more instructions are concurrently retired.

Abstract translation: 重排序缓冲器被配置成多行存储器，其中一行存储器包括足够的存储器，用于关于预定的最大数量的可同时发送的指令的指令结果。 只要调度一个或多个指令，就分配一行存储空间。 存储线保持分配，直到行内的每条指令准备退出，然后该线路被释放，因为一个或多个指令同时退出。