公开(公告)号：US07159786B2

公开(公告)日：2007-01-09

申请号：US10925882

申请日：2004-08-23

申请人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

发明人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

IPC分类号： G06K19/06

CPC分类号： G06K19/07747 ,  G06K19/07743 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.

摘要翻译： 数据载体卡具有扁平形式的卡体，并且具有凹槽，载体，布置在载体上的芯片并插入卡体的凹部中，外部接触元件布置在载体上并电连接到芯片通孔导体 并且覆盖与载体可操作地连接的凹部的盖，使得载体沿着凹部中的底部保持，其中外部接触元件和芯片布置在载体的同一侧上。

公开(公告)号：US07094648B2

公开(公告)日：2006-08-22

申请号：US11023041

申请日：2004-12-27

申请人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

IPC分类号： H01L21/8236

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。

公开(公告)号：US07087500B2

公开(公告)日：2006-08-08

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源极/漏极区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US07041545B2

公开(公告)日：2006-05-09

申请号：US10795611

申请日：2004-03-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

公开(公告)号：US20050242388A1

公开(公告)日：2005-11-03

申请号：US10835390

申请日：2004-04-30

申请人： Josef Willer ,  Frank Lau

发明人： Josef Willer ,  Frank Lau

IPC分类号： G11C16/02 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

公开(公告)号：US06960505B2

公开(公告)日：2005-11-01

申请号：US10706841

申请日：2003-11-12

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

摘要： A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

摘要翻译： 用于在源极区域和漏极区域上捕获电荷载流子的存储层在沟道上被中断，从而防止了俘获在源极区域和漏极区域上方的电荷载流子的扩散。 存储层被限制在源区域和漏极区域的面向通道的部分上的区域，并且被全部包埋在氧化物中。

公开(公告)号：US20050227426A1

公开(公告)日：2005-10-13

申请号：US10815223

申请日：2004-03-31

申请人： Joachim Deppe ,  Josef Willer

发明人： Joachim Deppe ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.

摘要翻译： 在包括电荷捕获存储器单元的存储单元阵列中，沿用于将相邻存储器单元的源极/漏极区域连接到位线的字线方向的局部互连通过在上部的半导体材料的侧壁上选择性沉积硅或多晶硅桥来形成 浅沟槽隔离物的电介质材料中的凹槽穿过字线。

公开(公告)号：US20050164456A1

公开(公告)日：2005-07-28

申请号：US11023041

申请日：2004-12-27

申请人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Kleint ,  Christoph Ludwig ,  Josef Willer

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

摘要翻译： 在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。 存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。 在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层 （18），其被设置用于字线，并且被图案化以形成字线。

公开(公告)号：US20050085037A1

公开(公告)日：2005-04-21

申请号：US11006049

申请日：2004-12-07

申请人： Christoph Kleint ,  Christoph Ludwig ,  Josef Willer ,  Joachim Deppe

发明人： Christoph Kleint ,  Christoph Ludwig ,  Josef Willer ,  Joachim Deppe

IPC分类号： H01L29/41 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

摘要翻译： 在沟槽被蚀刻到半导体材料之前，将导电位线层施加并图案化成彼此平行布置的部分，在这种情况下，在位线层（3,4）的图案化之后并且在蚀刻 引入注入用于限定结的位置，或者在用于源极/漏极区的n + H +型阱（19）的注入之后，位线层 （3,4）使用布置在半导体本体（1）上的蚀刻停止层（2）进行图案化。

公开(公告)号：US06777725B2

公开(公告)日：2004-08-17

申请号：US10171643

申请日：2002-06-14

申请人： Josef Willer ,  Herbert Palm

发明人： Josef Willer ,  Herbert Palm

IPC分类号： H01L29768

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.

摘要翻译： NROM存储器类型的集成存储器电路包括由具有低欧姆电阻的材料形成的凹陷位线。 通过将相对于用于存储单元阵列的外围控制电路的半导体衬底表面的位线凹进，可以在完美或几乎完美的平面上形成字线光刻，使得字线形成导致具有更高产量的生产 因此，单个集成存储器电路的成本较低。