公开(公告)号：US20090032869A1

公开(公告)日：2009-02-05

申请号：US12181692

申请日：2008-07-29

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

摘要翻译： 提供了一种半导体器件，其包括形成在半导体层中的第一晶体管和第二晶体管。 第一晶体管包括第一源极区域和与第一源极区域夹持第一栅电极的第一漏极区域。 第二晶体管包括LDD区和漂移区，其夹持具有LDD区的第二栅极，以及与漂移区相邻的第二漏极区，以将第二栅电极夹在第二源极区。 第一栅电极具有形成在其侧面上的第一侧壁，并且第二栅电极具有形成在其侧面上的第二侧壁。 沿着第一绝缘体的前者的宽度与第二绝缘体的宽度不同。

公开(公告)号：US20060097292A1

公开(公告)日：2006-05-11

申请号：US11261531

申请日：2005-10-31

申请人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Norio Yasuhara

发明人： Kazutoshi Nakamura ,  Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity type source region, a gate electrode formed between the first conductivity type source region and the first conductivity type drain region across an insulation film, and a second conductivity type contact layer formed adjacent to the first conductivity type source region, wherein the second conductivity type layer in the source region side has a higher impurity concentration than the impurity concentration of the second conductivity type layer in the drain region side.

摘要翻译： 半导体器件包括通过改变半导体衬底上的杂质浓度选择性地形成的第二导电类型层，形成在第二导电类型层上的第一导电型源极区，形成在第二导电类型层上的第一导电类型漏极区， 第一导电型源极区，形成在绝缘膜之间的第一导电型源极区域和第一导电型漏极区域之间的栅电极和与第一导电型源极区域相邻形成的第二导电型接触层，其中第二导电型源极区域 源极区侧的杂质浓度比漏区侧的第二导电型层的杂质浓度高。

公开(公告)号：US20130240947A1

公开(公告)日：2013-09-19

申请号：US13680849

申请日：2012-11-19

申请人： Tomoko Matsudai ,  Tsuneo Ogura

发明人： Tomoko Matsudai ,  Tsuneo Ogura

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/7397 ,  H01L27/0623 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6609 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

摘要： A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches.

摘要翻译： 一种半导体器件，形成在第一导电类型的衬底上，包括设置在衬底的第一面上的第二导电性的基底层，在基底层的一部分中具有较高掺杂量的阳极层，形成的IGBT区域 在基极层上，形成在阳极层上的二极管区域，从IGBT顶部延伸的沟槽和二极管区域延伸到衬底。 二极管区域所占的面积与IGBT区域所占的面积不同，但共享集电极和发射极。 二极管阳极层和发射电极之间的接触面积可以通过沟槽的布置进行调节。

公开(公告)号：US08507985B2

公开(公告)日：2013-08-13

申请号：US13052027

申请日：2011-03-18

申请人： Hirofumi Hirasozu ,  Kimihiko Deguchi ,  Manji Obatake ,  Tomoko Matsudai

发明人： Hirofumi Hirasozu ,  Kimihiko Deguchi ,  Manji Obatake ,  Tomoko Matsudai

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 μm. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region.

摘要翻译： 根据一个实施例，半导体器件包括半导体层，第一导电类型的第一基极区域，第二导电类型的第一源极区域，第一导电类型的第二基极区域，第一导电类型的第二基极区域， 第一导电类型，第二导电类型的漂移区，第二导电类型的漏极区，第一绝缘区，第二绝缘区，栅极氧化膜，第一栅电极，第二栅电极，第一主电极 电极和第二主电极。 这些构成元件设置在半导体层的表面上。 第一基极区域和第一绝缘区域之间的距离不大于1.8μm。 第一基极区域和第一绝缘区域之间的距离比第二基极区域和第二绝缘区域之间的距离短。

公开(公告)号：US08159036B2

公开(公告)日：2012-04-17

申请号：US12141386

申请日：2008-06-18

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L21/02

CPC分类号： H01L29/0847 ,  H01L21/2652 ,  H01L21/2658 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

摘要翻译： 第二导电类型的LDD层位于侧壁绝缘膜下面的半导体层的表面。 第二导电类型的源极层在与LDD层相邻的位置处形成在半导体层的表面中。 在半导体层的表面上，在与LDD层夹着栅电极的位置处形成第二导电类型的复层。 第二导电类型的漏极层在与复层层相邻的位置处形成在半导体层的表面中。 再次形成深度为半导体层表面的第一和第二杂质浓度的峰值。 第一杂质浓度的峰值小于第二杂质浓度的峰值。

公开(公告)号：US20110309439A1

公开(公告)日：2011-12-22

申请号：US13052254

申请日：2011-03-21

申请人： Tomoko Matsudai ,  Koichi Endo ,  Kumiko Sato ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Koichi Endo ,  Kumiko Sato ,  Norio Yasuhara

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1045 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region.

摘要翻译： 根据一个实施例，半导体器件包括半导体衬底，第一导电类型区域，第二导电型源极区域，栅极绝缘膜和栅极电极。 第一导电型区域设置在半导体衬底的上层部分中。 第二导电型源极区域和第二导电型漏极区域通过在第一导电类型区域的上层部分中彼此分离而布置。 栅极绝缘膜设置在半导体衬底上。 栅电极设置在栅极绝缘膜上。 与第一导电型区域中的栅电极正下方的区域对应的沟道区域中的杂质的有效浓度在栅极绝缘膜与沟道区域之间的界面处具有最大值，并且朝向沟道的下部逐渐减小 地区。

公开(公告)号：US20110303979A1

公开(公告)日：2011-12-15

申请号：US13052027

申请日：2011-03-18

申请人： Hirofumi HIRASOZU ,  Kimihiko Deguchi ,  Manji Obatake ,  Tomoko Matsudai

发明人： Hirofumi HIRASOZU ,  Kimihiko Deguchi ,  Manji Obatake ,  Tomoko Matsudai

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 μm. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region.

摘要翻译： 根据一个实施例，半导体器件包括半导体层，第一导电类型的第一基极区域，第二导电类型的第一源极区域，第一导电类型的第二基极区域，第一导电类型的第二基极区域， 第一导电类型，第二导电类型的漂移区，第二导电类型的漏极区，第一绝缘区，第二绝缘区，栅极氧化膜，第一栅电极，第二栅电极，第一主电极 电极和第二主电极。 这些构成元件设置在半导体层的表面上。 第一基极区域和第一绝缘区域之间的距离不大于1.8μm。 第一基极区域和第一绝缘区域之间的距离比第二基极区域和第二绝缘区域之间的距离短。

公开(公告)号：US20100159659A1

公开(公告)日：2010-06-24

申请号：US12716352

申请日：2010-03-03

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。