公开(公告)号：US20100244934A1

公开(公告)日：2010-09-30

申请号：US12411494

申请日：2009-03-26

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： G11C5/14 ,  H01L29/06 ,  G06F17/50 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L27/1203

摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

摘要翻译： 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US20100156510A1

公开(公告)日：2010-06-24

申请号：US12342488

申请日：2008-12-23

申请人： Alan B. Botula ,  Edward J. Nowak ,  James A. Slinkman

发明人： Alan B. Botula ,  Edward J. Nowak ,  James A. Slinkman

IPC分类号： H01L21/265 ,  H03K3/01 ,  H01L29/786 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L21/76224 ,  H01L21/76251 ,  H01L27/1203

摘要： First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions, thereby reducing of harmonic signals in the semiconductor devices above and enhancing the performance of the semiconductor devices as a radio-frequency (RF) switch.

摘要翻译： 直接在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成具有与底部半导体层相同类型掺杂的第一掺杂半导体区域和具有相反类型掺杂的第二掺杂半导体区域。 第一掺杂半导体区域和第二掺杂半导体区域以不足以由于少数载流子正向偏置注入底部半导体层而引起过大电流的电压而相对于底部半导体层电接地或正向偏置，即 ，电位差不超过0.6V至0.8V。 通过顶部半导体层上的半导体器件中的电信号在感应电荷层中形成的电荷通过连接到第一和第二掺杂半导体区域的电触点排出，从而减少上述半导体器件中的谐波信号并增强性能 的半导体器件作为射频（RF）开关。

公开(公告)号：US07507591B2

公开(公告)日：2009-03-24

申请号：US11160086

申请日：2005-06-08

申请人： George W. Banke, Jr. ,  Andrew Deering ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James Robert ,  James A. Slinkman

发明人： George W. Banke, Jr. ,  Andrew Deering ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James Robert ,  James A. Slinkman

IPC分类号： H01L21/00 ,  G01M19/00

CPC分类号： A61M1/0058 ,  A61M1/0084 ,  G01N1/32 ,  G01R31/2898

摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.

摘要翻译： 通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。 用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。 然后可以使用原子力显微镜（AFM）对印记进行成像。 该图像可用于测量结构的底面。

公开(公告)号：US06946710B2

公开(公告)日：2005-09-20

申请号：US10687295

申请日：2003-10-16

申请人： Lyndon R. Logan ,  James A. Slinkman

发明人： Lyndon R. Logan ,  James A. Slinkman

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/772

CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L27/0921

摘要： A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and align to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the P-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

摘要翻译： 一种形成具有改进的泄漏控制的半导体器件的方法，包括：提供半导体衬底; 在衬底中形成沟槽; 在沟槽的底部下方的衬底中形成泄漏停止注入，并且在沟槽的侧壁下方并对齐; 用绝缘体填充沟槽; 以及在所述衬底中与所述沟槽的相对侧壁相邻并与之相接触的衬底上形成N阱（或P阱），所述N阱（或P阱）在所述沟槽下延伸并形成所述沟槽的上部 与泄漏停止注入的隔离结，隔离结的上部完全位于沟槽下方。 泄漏控制植入物与沟槽侧壁自对准。

公开(公告)号：US06822311B2

公开(公告)日：2004-11-23

申请号：US10413301

申请日：2003-04-15

申请人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

发明人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshihura Furukawa ,  Jeffrey D. Gilbert ,  Glenn R. Miller ,  James A. Slinkman

IPC分类号： H01L2900

CPC分类号： H01L21/2253 ,  C21D1/04 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/326

摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

摘要翻译： 一种用于在半导体器件中形成期望的接合剖面的方法。 将至少一种掺杂剂引入到半导体衬底中。 所述至少一种掺杂剂通过对所述半导体衬底和所述至少一种掺杂物退火而在所述半导体衬底中扩散，同时将所述半导体衬底暴露于电场。

公开(公告)号：US6139759A

公开(公告)日：2000-10-31

申请号：US256261

申请日：1999-02-23

申请人： Lambert A. Doezema ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James M. Never ,  James A. Slinkman

发明人： Lambert A. Doezema ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James M. Never ,  James A. Slinkman

IPC分类号： C25F3/08 ,  G01B7/34 ,  G01R31/02

CPC分类号： G01Q60/40 ,  B82Y35/00 ,  G01Q60/30 ,  Y10S977/879

摘要： A micromechanical sensor probe for a scanned-probe tool comprising a silicon probe and a coating of a refractory metal silicide formed at least on the tip of the probe. Titanium silicide is preferred. A method for manufacturing such a probe includes the steps of, first, providing a silicon cantilever and tip combination and, second, forming a refractory metal silicide on at least the tip of the cantilever and tip combination. This second step of the method includes removing any remnant oxide from the tip, stabilizing the cantilever and tip combination on a carrier, depositing a refractory metal on the silicon tip, heating the cantilever and tip combination in an ambient free of oxygen to react chemically the refractory metal on and the silicon of the tip, selectively etching any unreacted refractory metal from the tip, and annealing the cantilever and tip combination in an ambient free of oxygen. The method may also include, as a final step, removing any unreacted refractory metal from the tip.

摘要翻译： 一种用于扫描探针工具的微机械传感器探针，其包括硅探针和至少形成在探针尖端上的难熔金属硅化物的涂层。 硅化钛是优选的。 用于制造这种探针的方法包括以下步骤：首先提供硅悬臂和尖端组合，其次，在悬臂和尖端组合的至少尖端上形成难熔金属硅化物。 该方法的第二步骤包括从尖端去除任何残余氧化物，将悬臂和尖端组合稳定在载体上，将难熔金属沉积在硅尖端上，在不含氧的环境中加热悬臂和尖端组合以化学反应 难熔金属和尖端的硅，从尖端选择性地蚀刻任何未反应的难熔金属，并且在没有氧的环境中退火悬臂和尖端组合。 作为最后的步骤，还可以包括从尖端去除任何未反应的难熔金属。