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    Method of manufacturing silicided silicon microtips for scanning probe microscopy
    2.
    发明授权
    Method of manufacturing silicided silicon microtips for scanning probe microscopy 失效
    制造用于扫描探针显微镜的硅化硅微尖头的方法

    公开(公告)号：US6139759A

    公开(公告)日：2000-10-31

    申请号：US256261

    申请日：1999-02-23

    申请人： Lambert A. Doezema ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James M. Never ,  James A. Slinkman

    发明人： Lambert A. Doezema ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James M. Never ,  James A. Slinkman

    IPC分类号： C25F3/08 ,  G01B7/34 ,  G01R31/02

    CPC分类号： G01Q60/40 ,  B82Y35/00 ,  G01Q60/30 ,  Y10S977/879

    摘要： A micromechanical sensor probe for a scanned-probe tool comprising a silicon probe and a coating of a refractory metal silicide formed at least on the tip of the probe. Titanium silicide is preferred. A method for manufacturing such a probe includes the steps of, first, providing a silicon cantilever and tip combination and, second, forming a refractory metal silicide on at least the tip of the cantilever and tip combination. This second step of the method includes removing any remnant oxide from the tip, stabilizing the cantilever and tip combination on a carrier, depositing a refractory metal on the silicon tip, heating the cantilever and tip combination in an ambient free of oxygen to react chemically the refractory metal on and the silicon of the tip, selectively etching any unreacted refractory metal from the tip, and annealing the cantilever and tip combination in an ambient free of oxygen. The method may also include, as a final step, removing any unreacted refractory metal from the tip.

    摘要翻译： 一种用于扫描探针工具的微机械传感器探针，其包括硅探针和至少形成在探针尖端上的难熔金属硅化物的涂层。 硅化钛是优选的。 用于制造这种探针的方法包括以下步骤：首先提供硅悬臂和尖端组合，其次，在悬臂和尖端组合的至少尖端上形成难熔金属硅化物。 该方法的第二步骤包括从尖端去除任何残余氧化物，将悬臂和尖端组合稳定在载体上，将难熔金属沉积在硅尖端上，在不含氧的环境中加热悬臂和尖端组合以化学反应 难熔金属和尖端的硅，从尖端选择性地蚀刻任何未反应的难熔金属，并且在没有氧的环境中退火悬臂和尖端组合。 作为最后的步骤，还可以包括从尖端去除任何未反应的难熔金属。

    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES
    5.
    发明申请
    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES 有权
    用于检测集成设备中的局部机械应力的系统和方法

    公开(公告)号：US20090219508A1

    公开(公告)日：2009-09-03

    申请号：US12039830

    申请日：2008-02-29

    申请人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    发明人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    IPC分类号： G01B11/16

    CPC分类号： G01B21/32 ,  G01Q60/30

    摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.

    摘要翻译： 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于 光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

    System and method for detecting local mechanical stress in integreated devices
    6.
    发明授权
    System and method for detecting local mechanical stress in integreated devices 有权
    用于检测集成设备中局部机械应力的系统和方法

    公开(公告)号：US07944550B2

    公开(公告)日：2011-05-17

    申请号：US12039830

    申请日：2008-02-29

    申请人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    发明人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    IPC分类号： G01B11/16

    CPC分类号： G01B21/32 ,  G01Q60/30

    摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.

    摘要翻译： 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于 光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
    8.
    发明授权
    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region 有权
    绝缘体上半导体基板和结构包括多阶射频谐波抑制区域

    公开(公告)号：US08299537B2

    公开(公告)日：2012-10-30

    申请号：US12369099

    申请日：2009-02-11

    申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L21/70

    CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

    摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
    10.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
    用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法

    公开(公告)号：US20110127529A1

    公开(公告)日：2011-06-02

    申请号：US12627343

    申请日：2009-11-30

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。