公开(公告)号：US08194461B2

公开(公告)日：2012-06-05

申请号：US12985427

申请日：2011-01-06

申请人： Yasukazu Kosaki ,  Noboru Shibata

发明人： Yasukazu Kosaki ,  Noboru Shibata

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

公开(公告)号：US20120092929A1

公开(公告)日：2012-04-19

申请号：US13329671

申请日：2011-12-19

申请人： Noboru Shibata ,  Kenichi Imamiya

发明人： Noboru Shibata ,  Kenichi Imamiya

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30

摘要： A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

摘要翻译： 存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。 选择晶体管选择字线。 控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储单元的写入，读取和擦除操作。 选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压第一负电压）被提供给所选择的字线，并且第二电压被提供给未选择的 字线在读操作。

公开(公告)号：US20120054416A1

公开(公告)日：2012-03-01

申请号：US13050431

申请日：2011-03-17

申请人： Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G06F12/02

CPC分类号： G11C11/5628

摘要： According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y

摘要翻译： 根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。 存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序 到记忆体细胞。 控制器包括基于x位产生y位（y为整数和y

公开(公告)号：US20110238889A1

公开(公告)日：2011-09-29

申请号：US12884648

申请日：2010-09-17

申请人： Makoto Miakashi ,  Noboru Shibata

发明人： Makoto Miakashi ,  Noboru Shibata

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3436

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列由以矩阵图案排列的多个存储单元组成。 控制电路在第二存储器单元中设置第一标志数据，以便将数据写入存储单元阵列的多个第一存储单元，第二存储单元已经与第一存储器单元同时被选择， 在从第一存储器单元读取数据之前，在第二存储单元中设置第一标志数据，并且如果第一标志数据未被设置在第二存储器单元中，则不从第一存储器单元读取数据并输出第一逻辑电平的数据， 并且如果第一标志数据被设置在第二存储器单元中，则从第一存储器单元读取数据。

公开(公告)号：US07995392B2

公开(公告)日：2011-08-09

申请号：US12332681

申请日：2008-12-11

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

摘要： In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

摘要翻译： 在存储单元阵列中，连接到多个字线和多个位线的多个存储单元被布置成矩阵。 控制电路控制所述多个字线和所述多个位线的电位。 在擦除操作中，控制电路使用第一擦除电压同时擦除所述多个存储单元的n个存储单元（n为等于或大于2的自然数），执行使用 第一验证电平，找到超过第一验证电平的单元数k（k＆nlE; n），根据数k确定第二擦除电压，并使用第二擦除电压再次执行擦除操作。

公开(公告)号：US07933152B2

公开(公告)日：2011-04-26

申请号：US12641401

申请日：2009-12-18

申请人： Noboru Shibata ,  Kenichi Imamiya

发明人： Noboru Shibata ,  Kenichi Imamiya

IPC分类号： G11C16/06

CPC分类号： G11C16/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30

摘要： A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

摘要翻译： 存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。 选择晶体管选择字线。 控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储器单元的写入，读取和擦除操作。 选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压≥第一负电压）被提供给所选择的字线，并且第二电压被提供给非易失性存储器， 在读取操作中选择字线。

公开(公告)号：US20110069545A1

公开(公告)日：2011-03-24

申请号：US12882507

申请日：2010-09-15

申请人： Takuya FUTATSUYAMA ,  Yoshihisa Kondo ,  Noboru Shibata

发明人： Takuya FUTATSUYAMA ,  Yoshihisa Kondo ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C8/00 ,  G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.

摘要翻译： 根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个 记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。 存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。 当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

公开(公告)号：US07908529B2

公开(公告)日：2011-03-15

申请号：US12371659

申请日：2009-02-16

申请人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

发明人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

IPC分类号： G11C29/00 ,  G11C16/04 ,  H03M13/00

CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

公开(公告)号：US20110058416A1

公开(公告)日：2011-03-10

申请号：US12948256

申请日：2010-11-17

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/3459

摘要： A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller, and is a natural number equal to 3 or larger) bits stored in the memory cells into data of h (h is equal to k or larger, and is a natural number equal to 2 or larger) bits on the basis of a conversion rule.

摘要翻译： 存储单元阵列包括多个存储单元，其中n（n是等于3或更大的自然数）单元被同时写入。 控制电路控制存储单元阵列。 A转换电路将存储在存储单元中的k（k等于或小于等于3的自然数）构成的数据转换为h（h等于k或更大）的数据，并且是 自然数等于2或更大）比特。

公开(公告)号：US07894259B2

公开(公告)日：2011-02-22

申请号：US12576638

申请日：2009-10-09

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/22 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/70 ,  G11C29/832 ,  G11C2211/5621 ,  G11C2211/5641

摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

摘要翻译： 存储单元阵列具有第一和第二存储区域。 第一存储区具有由地址信号选择的存储元件。 第二存储区域具有由控制信号选择的存储元件。 控制电路具有熔丝元件。 当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。