公开(公告)号：US20160293491A1

公开(公告)日：2016-10-06

申请号：US14696494

申请日：2015-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract translation: 翅片结构切割过程包括以下步骤。 四个翅片结构形成在基板中，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。

公开(公告)号：US20160276465A1

公开(公告)日：2016-09-22

申请号：US14658246

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3115

CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/665

Abstract: The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively. An etching process is then performed to form a plurality of trenches in the first dielectric layer, and a conductive layer is filled in each trench to form a plurality of contacts in the first dielectric layer.

Abstract translation: 本发明提供一种半导体器件的制造方法，包括提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个栅极，至少一个硬掩模设置在顶部 栅极的表面，并且至少两个间隔物分别设置在栅极的两侧。 接下来，对硬掩模和第一电介质层进行覆盖注入工艺，以在第一电介质层中，在硬掩模和间隔物中分别形成离子富集区。 然后执行蚀刻工艺以在第一介电层中形成多个沟槽，并且在每个沟槽中填充导电层以在第一介电层中形成多个触点。

公开(公告)号：US09406805B2

公开(公告)日：2016-08-02

申请号：US14749648

申请日：2015-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Rai-Min Huang ,  Sheng-Huei Dai ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L29/7853 ,  H01L21/02647 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L2029/7858

Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

公开(公告)号：US09385193B2

公开(公告)日：2016-07-05

申请号：US14288369

申请日：2014-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。

公开(公告)号：US20150064929A1

公开(公告)日：2015-03-05

申请号：US14018447

申请日：2013-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Shih-Hung Tsai ,  Rai-Min Huang ,  Yu-Ting Lin ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer.

Abstract translation: 间隙填充的方法包括提供其中形成有多个间隙的基板。 然后，进行原位蒸汽发生氧化，以在衬底上形成氧化物衬垫。 形成氧化物衬垫以覆盖间隙的表面。 随后，进行高纵横比处理以在氧化物衬垫上形成氧化物保护层。 在形成氧化物保护层之后，进行可流动的化学气相沉积以在氧化物保护层上形成填充氧化物。 更重要的是，间隙填充有氧化物填充层。

公开(公告)号：US20150014808A1

公开(公告)日：2015-01-15

申请号：US13939204

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Rai-Min Huang ,  I-Ming Tseng ,  Yu-Ting Lin ,  Chien-Ting Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/66818 ,  H01L29/7853

Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.

Abstract translation: 半导体结构的制造方法至少包括以下步骤。 首先，在基板上形成具有预定布局图案的图案掩模。 然后将布局图案转移到基底下方，以在基底中形成至少一个鳍状结构。 随后，在鳍状结构周围形成浅沟槽隔离结构。 之后，进行蒸汽氧化处理，使从浅沟槽隔离突出的鳍状结构氧化，并在其表面形成氧化物层。 最后，氧化层被完全去除。