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公开(公告)号：US20120127794A1
公开(公告)日：2012-05-24
申请号：US12949876
申请日：2010-11-19
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/26
摘要： Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
摘要翻译： 公开了用于程序验证，程序验证电路和存储器件的方法。 用于程序验证的一种这样的方法包括为多个计数值生成斜坡电压。 斜坡电压被施加到被程序验证的存储器单元的控制栅极。 将每个计数值的至少一部分与存储器单元的目标阈值电压的指示进行比较。 当计数值的至少一部分等于目标阈值电压指示的指示时，感测电路用于检查存储器单元是否已被计数产生的电压激活。 如果存储单元已被激活，则设置禁止锁存器以禁止存储器单元的进一步编程。 如果存储单元没有被电压激活，则存储单元被另一编程脉冲偏置。
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公开(公告)号：US20110299333A1
公开(公告)日：2011-12-08
申请号：US12795202
申请日：2010-06-07
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described.
摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括基于处于擦除状态的存储器单元的阈值电压将不同的电压施加到与不同存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。
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公开(公告)号：US20110255344A1
公开(公告)日：2011-10-20
申请号：US13173171
申请日：2011-06-30
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
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公开(公告)号：US20110255343A1
公开(公告)日：2011-10-20
申请号：US13170420
申请日：2011-06-28
IPC分类号： G11C16/10
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件和存储器件的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US07983088B2
公开(公告)日：2011-07-19
申请号：US12477314
申请日：2009-06-03
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件，存储器件和存储器系统的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US20110134701A1
公开(公告)日：2011-06-09
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译： 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲步长电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US20100246270A1
公开(公告)日：2010-09-30
申请号：US12795764
申请日：2010-06-08
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
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公开(公告)号：US20100246265A1
公开(公告)日：2010-09-30
申请号：US12410696
申请日：2009-03-25
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 公开了存储器件和方法，以便于基于存储在存储器件中的擦除操作周期计数器值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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公开(公告)号：US07751246B2
公开(公告)日：2010-07-06
申请号：US12177972
申请日：2008-07-23
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
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公开(公告)号：US20100165739A1
公开(公告)日：2010-07-01
申请号：US12718290
申请日：2010-03-05
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译： 本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。 该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平 并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。
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