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公开(公告)号：US08174897B2
公开(公告)日：2012-05-08
申请号：US13170420
申请日：2011-06-28
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件和存储器件的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US20100157685A1
公开(公告)日：2010-06-24
申请号：US12477314
申请日：2009-06-03
IPC分类号： G11C16/04
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件，存储器件和存储器系统的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US20110255343A1
公开(公告)日：2011-10-20
申请号：US13170420
申请日：2011-06-28
IPC分类号： G11C16/10
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件和存储器件的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US07983088B2
公开(公告)日：2011-07-19
申请号：US12477314
申请日：2009-06-03
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件，存储器件和存储器系统的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US09436402B1
公开(公告)日：2016-09-06
申请号：US13449082
申请日：2012-04-17
申请人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F11/263 , G06F3/06 , G11C16/06
CPC分类号： G06F17/30495 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.
摘要翻译： 公开了用于模式匹配的方法和装置。 在至少一个实施例中，通过读取存储器页面，并将读取的页面与在逻辑操作中要搜索的模式进行比较来实现模式检查。 在至少另一个实施例中，要搜索的图案被存储在使用两个寄存器条目存储图案的每个位的寄存器中，并且使用阵列的两个单元存储阵列数据的每一位。
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公开(公告)号：US06584035B2
公开(公告)日：2003-06-24
申请号：US10032375
申请日：2001-12-21
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C7/1048 , G11C8/10 , G11C2207/002
摘要： Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.
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7.发明授权Low voltage flash EEPROM C-cell using fowler-nordheim tunneling 失效低压闪存EEPROM C-cell使用fowler-nordheim隧道
公开(公告)号：US5557569A
公开(公告)日：1996-09-17
申请号：US453474
申请日：1995-05-25
申请人： Michael C. Smayling , Giulio G. Marotta , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
发明人： Michael C. Smayling , Giulio G. Marotta , Iano D'Arrigo , Giovanni Santin , Georges Falessi , Mousumi Bhat
IPC分类号： G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C16/0416 , G11C16/0433 , G11C16/08 , H01L27/115
摘要： A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.
摘要翻译： 低电压快闪EEPROM X-Cell包括构成非对称浮动栅极存储单元的存储单元晶体管阵列（24），其中仅在存储单元（24）的一侧实现编程。 每个存储器单元（24）的编程侧在节点（30）处连接到多个列线（28）中的一个。 每个节点（30）共享两个存储器单元（24）的两个存储器单元（24）的非编程侧的编程侧。 每个存储器单元（24）的控制栅极连接到与阵列的行相关联的字线（26）。 闪存写入所有存储单元（24），列线（38）连接到负中等电压，行线（26）连接到正中压。 为了选择性地擦除存储器单元（24）中的一个，与选择存储单元晶体管的编程侧相关联的列线（28）连接到正的中间电压，并且相关的线路（26）连接到正的读取电压 。 剩下的字线连接到负的读取电压，剩余的列线（28）连接到零伏电平。
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公开(公告)号：US6118706A
公开(公告)日：2000-09-12
申请号：US373436
申请日：1999-08-11
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16 , G11C16/30
摘要： FLASH Memory hardware Block or sector Clear Operation using a single block or sector operation without using "byte-mode" processing is described. This hardware Block or sector Clear operation does not use avalanche injection, and has several distinct advantages, including programming simplicity, increased device reliability and yield. Use of the hardware block or sector clear operation described here results in increased programming speed, faster chip testing, and faster write/erase cycling compared to the normal operations of prior art.
摘要翻译： 闪存存储器硬件块或扇区清除在不使用“字节模式”处理的情况下使用单个块或扇区操作进行操作。 该硬件块或扇区清除操作不使用雪崩注入，并且具有几个显着的优点，包括编程简单性，增加的设备可靠性和产量。 与现有技术的正常操作相比，使用这里描述的硬件块或扇区清除操作导致增加的编程速度，更快的芯片测试和更快的写入/擦除循环。
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公开(公告)号：US06262914B1
公开(公告)日：2001-07-17
申请号：US09372266
申请日：1999-08-11
IPC分类号： G11C1604
CPC分类号： G11C16/0491
摘要： Segmentation of FLASH Memory arrays allows the global and local bit lines to be isolated, greatly reducing global bit line capacitance, reducing bit line stress, and eliminating boot block disturb effects. Reduction in bit line capacitance also results in fast access time greatly improving the ability to implement larger arrays without paying severe access time penalties.
摘要翻译： FLASH存储器阵列的分段允许全局和局部位线隔离，大大降低了全局位线电容，降低了位线应力，并消除了引导块干扰效应。 减少位线电容还导致快速访问时间大大提高了实现更大阵列的能力，而不会严重的访问时间损失。
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公开(公告)号：US06191976B1
公开(公告)日：2001-02-20
申请号：US09372730
申请日：1999-08-11
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C16/3436
摘要： FLASH Memory sense amplifier reference circuit with weighted dummy loads is used to balance and bias the sense amplifier during erasing, programming, and verification such that the resulting robust stored logic states can meet more stringent pass-fail verify “1” or verify “0” tests. Programming in this manner guarantees logic states which meet full operating temperature and full power supply tolerances requirements.
摘要翻译： 闪存具有加权虚拟负载的存储器读出放大器参考电路用于在擦除，编程和验证期间平衡和偏置读出放大器，使得得到的鲁棒存储逻辑状态可以满足更严格的通过失败验证“1”或验证“0” 测试。 以这种方式进行编程可确保满足全部工作温度和全部电源容限要求的逻辑状态。
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