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公开(公告)号：US08036035B2
公开(公告)日：2011-10-11
申请号：US12410696
申请日：2009-03-25
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 公开了存储器件和方法，以便于基于存储在存储器件中的擦除操作周期计数器值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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公开(公告)号：US20100246265A1
公开(公告)日：2010-09-30
申请号：US12410696
申请日：2009-03-25
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 公开了存储器件和方法，以便于基于存储在存储器件中的擦除操作周期计数器值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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公开(公告)号：US08358538B2
公开(公告)日：2013-01-22
申请号：US13268158
申请日：2011-10-07
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 存储器件，用于根据存储在存储器件中的擦除操作周期计数值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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公开(公告)号：US20120026792A1
公开(公告)日：2012-02-02
申请号：US13268158
申请日：2011-10-07
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 存储器件，用于根据存储在存储器件中的擦除操作周期计数值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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公开(公告)号：US20100122016A1
公开(公告)日：2010-05-13
申请号：US12269766
申请日：2008-11-12
申请人： Giulio Marotta , Luca De Santis , Tommaso Vali
发明人： Giulio Marotta , Luca De Santis , Tommaso Vali
CPC分类号： G11C16/16 , G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.
摘要翻译： 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。
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公开(公告)号：US20080298130A1
公开(公告)日：2008-12-04
申请号：US12188377
申请日：2008-08-08
申请人： Luca De Santis , Luigi Pilolli
发明人： Luca De Santis , Luigi Pilolli
IPC分类号： G11C16/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0875 , G06F12/0893 , G06F13/1668 , G06F2212/2022 , G06F2212/452 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/16 , G11C11/4074 , G11C11/4096 , G11C16/06 , G11C16/10 , G11C2207/2245 , Y02D10/13 , Y02D10/14
摘要： A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.
摘要翻译： 存储器件分布式控制器电路在多个存储器控制器之间分配存储器控制功能。 主控制器接收解释命令，并根据命令激活适当的从控制器。 从控制器可以包括耦合到并控制数据高速缓存的数据高速缓存控制器和耦合到并控制模拟电压产生电路的模拟控制器。 相应的控制器具有适当的软件/固件指令，其确定相应控制器响应于所接收的命令所采取的响应。
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公开(公告)号：US20070211529A1
公开(公告)日：2007-09-13
申请号：US11508728
申请日：2006-08-23
申请人： Luca De Santis , Luigi Pilolli
发明人： Luca De Santis , Luigi Pilolli
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0875 , G06F12/0893 , G06F13/1668 , G06F2212/2022 , G06F2212/452 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/16 , G11C11/4074 , G11C11/4096 , G11C16/06 , G11C16/10 , G11C2207/2245 , Y02D10/13 , Y02D10/14
摘要： A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.
摘要翻译： 存储器件分布式控制器电路在多个存储器控制器之间分配存储器控制功能。 主控制器接收解释命令，并根据命令激活适当的从控制器。 从控制器可以包括耦合到并控制数据高速缓存的数据高速缓存控制器和耦合到并控制模拟电压产生电路的模拟控制器。 相应的控制器具有适当的软件/固件指令，其确定相应控制器响应于所接收的命令所采取的响应。
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公开(公告)号：US06671206B2
公开(公告)日：2003-12-30
申请号：US10229399
申请日：2002-08-27
申请人： Tommaso Vali , Luca De Santis
发明人： Tommaso Vali , Luca De Santis
IPC分类号： G11C1626
摘要： Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.
摘要翻译： 用于感测浮栅存储器单元的编程状态的感测装置适用于使用能够显着高于在感测操作期间在局部位线上实现的最大电位的电源电位的低功率存储器件。 这样的感测装置包括选择性地耦合到浮动栅极存储器单元的输入节点和用于提供指示浮动栅极存储器单元的编程状态的输出信号的输出节点。 这种感测装置还包括耦合在预充电路径和感测装置的输入节点之间的反馈回路。 反馈环路限制了在感测装置的输入节点处实现的电位电平，从而限制了感测期间由位线实现的电位电平。
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公开(公告)号：US20190042156A1
公开(公告)日：2019-02-07
申请号：US15986804
申请日：2018-05-22
申请人： Luca De Santis , Tommaso Vali , Luca Nubile , Ricardo Cardinali , Maria L. Gallese , Cristina Lattaro
发明人： Luca De Santis , Tommaso Vali , Luca Nubile , Ricardo Cardinali , Maria L. Gallese , Cristina Lattaro
IPC分类号： G06F3/06
摘要： Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.
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公开(公告)号：US09436402B1
公开(公告)日：2016-09-06
申请号：US13449082
申请日：2012-04-17
申请人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F11/263 , G06F3/06 , G11C16/06
CPC分类号： G06F17/30495 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.
摘要翻译： 公开了用于模式匹配的方法和装置。 在至少一个实施例中，通过读取存储器页面，并将读取的页面与在逻辑操作中要搜索的模式进行比较来实现模式检查。 在至少另一个实施例中，要搜索的图案被存储在使用两个寄存器条目存储图案的每个位的寄存器中，并且使用阵列的两个单元存储阵列数据的每一位。
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