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61.发明授权公开(公告)号：US06707117B1
公开(公告)日：2004-03-16
申请号：US10285235
申请日：2002-10-31
IPC分类号： H01C2976
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.
摘要翻译： 在半导体结构中，单个器件或不同器件的区域之间的互连通过形成跨越要互连的区域的金属插塞来实现，其中插塞由在结构上形成硅化物层所用的金属形成。 在蚀刻之前，将金属掩盖在所需区域中，以留下金属塞。
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公开(公告)号：US06667867B2
公开(公告)日：2003-12-23
申请号：US09767934
申请日：2001-01-23
IPC分类号： H02H900
CPC分类号： H02H9/046
摘要： In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a BJT acting as an avalanche diode is reduced by injecting current into the base of the BJT. This is achieved through the use of a capacitor connected between Vdd and the base of the avalanche BJT to speed up the switching of the protection circuit.
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公开(公告)号：US06560081B1
公开(公告)日：2003-05-06
申请号：US09690558
申请日：2000-10-17
IPC分类号： H02H900
CPC分类号： H02H9/046 , H01L27/0259 , H01L2924/0002 , H02H3/006 , H01L2924/00
摘要： An ESD protection circuit that can be easily configured to provide ESD event protection against a range of ESD event voltages. The circuit is also compatible with high frequency ICs. The ESD protection circuit includes an input terminal configured to receive an ESD event signal and a diode sub-circuit. The diode sub-circuit includes at least one diode (e.g., either a single diode or a plurality of diodes connected in series or parallel configuration), a diode input node and a diode output node. The diode sub-circuit is configured to receive an ESD event signal from the input terminal and to operate under forward bias conditions to provide a diode output signal at the diode output node. The circuit also includes a bipolar junction transistor (e.g., a Si—Ge bipolar junction transistor) with a base, a collector and an emitter. The emitter is configured to receive the ESD event signal from the input terminal, while the base is configured to receive the diode output signal from the diode output node. A resistor, with a resistor input node, a resistor output node and an output terminal, is also included in the circuit. The resistor input node is electrically connected to the diode output node and the output terminal is connected to the resistor output node, the emitter and ground. By predetermining the electrical characteristics (e.g., forward bias voltage) and number of diodes in the diode sub-circuit, the circuit can be adapted to provide ESD protection against a range of ESD event voltages.
摘要翻译： ESD保护电路可以轻松配置，以提供ESD事件保护，防止一系列ESD事件电压。 该电路还兼容高频IC。 ESD保护电路包括被配置为接收ESD事件信号的输入端子和二极管子电路。 二极管子电路包括至少一个二极管（例如，串联或并联配置连接的单个二极管或多个二极管），二极管输入节点和二极管输出节点。 二极管子电路被配置为从输入端子接收ESD事件信号并且在正向偏置条件下操作以在二极管输出节点处提供二极管输出信号。 该电路还包括具有基极，集电极和发射极的双极结型晶体管（例如，Si-Ge双极结型晶体管）。 发射极被配置为从输入端子接收ESD事件信号，而基极配置为从二极管输出节点接收二极管输出信号。 电路中还包括一个带有电阻输入节点的电阻，一个电阻输出节点和一个输出端子。 电阻输入节点电连接到二极管输出节点，输出端子连接到电阻输出节点，发射极和地。 通过预先确定二极管子电路中的电特性（例如，正向偏置电压）和二极管的数量，该电路可适用于针对一系列ESD事件电压提供ESD保护。
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64.发明授权Triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes 有权具有大于待受保护节点上的直流偏置电压的保持电压的三端双向可控硅开关公开(公告)号：US06541801B1
公开(公告)日：2003-04-01
申请号：US09782389
申请日：2001-02-12
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , H01L29/87
摘要： The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.
摘要翻译： 三端双向可控硅开关元件的保持电压（操作所需的最小电压）增加到大于被保护节点上的直流偏置的值。 通过在每个p +区域和被保护节点之间插入电压降来增加保持电压。 因此，三端双向可控硅开关可用于为电源引脚提供ESD保护。
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公开(公告)号：US07978519B2
公开(公告)日：2011-07-12
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译： 一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极 区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。
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公开(公告)号：US20110007574A1
公开(公告)日：2011-01-13
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译： 一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极 在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开， 包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。
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67.发明授权公开(公告)号：US07233521B1
公开(公告)日：2007-06-19
申请号：US11078761
申请日：2005-03-11
IPC分类号： G11C11/34
CPC分类号： G11C27/005 , G11C11/5621 , G11C16/0441 , G11C16/10
摘要： A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.
摘要翻译： 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间，第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。
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公开(公告)号：US07042763B1
公开(公告)日：2006-05-09
申请号：US10895711
申请日：2004-07-08
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C2216/10
摘要： A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.
摘要翻译： 一种选择性地编程非易失性存储单元的方法，其中使用多个编程电压来获得所选择用于编程的单元的存储节点上的期望电压，而未选定单元的存储节点保持不受干扰。
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69.发明授权Memory cell with a capacitive structure as a control gate and method of forming the memory cell 有权具有电容结构的存储单元作为控制栅极和形成存储单元的方法公开(公告)号：US06806529B1
公开(公告)日：2004-10-19
申请号：US10356422
申请日：2003-01-30
申请人： Peter J. Hopper , Yuri Mirgorodski , Andy Strachan
发明人： Peter J. Hopper , Yuri Mirgorodski , Andy Strachan
IPC分类号： H01L2972
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.
摘要翻译： 在电可编程非易失性存储单元中，高密度电容结构的第一端子电连接到导电结构以形成浮置栅极/第一电极，而电容结构的第二端子用作控制栅极， 提供具有高总体电容耦合比，相对小的面积和高电压容限的电池。
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70.发明申请Gas Detector that Utilizes an Electric Field to Assist in the Collection and Removal of Gas Molecules 有权气体探测器利用电场来辅助气体分子的收集和去除公开(公告)号：US20120060587A1
公开(公告)日：2012-03-15
申请号：US12880464
申请日：2010-09-13
CPC分类号： G01N27/4141
摘要： A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
摘要翻译： 基于半导体的气体检测器增强了气体分子的收集，并且还提供了一种独立的装置，用于通过利用一个或多个电场来将气体分子输送到和远离具有高渗透性的金属材料 气体分子。
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