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1.发明授权Memory cell with a capacitive structure as a control gate and method of forming the memory cell 有权具有电容结构的存储单元作为控制栅极和形成存储单元的方法公开(公告)号：US06806529B1
公开(公告)日：2004-10-19
申请号：US10356422
申请日：2003-01-30
申请人： Peter J. Hopper , Yuri Mirgorodski , Andy Strachan
发明人： Peter J. Hopper , Yuri Mirgorodski , Andy Strachan
IPC分类号： H01L2972
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.
摘要翻译： 在电可编程非易失性存储单元中，高密度电容结构的第一端子电连接到导电结构以形成浮置栅极/第一电极，而电容结构的第二端子用作控制栅极， 提供具有高总体电容耦合比，相对小的面积和高电压容限的电池。
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公开(公告)号：US07978519B2
公开(公告)日：2011-07-12
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译： 一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极 区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。
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公开(公告)号：US20110007574A1
公开(公告)日：2011-01-13
申请号：US12884519
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.
摘要翻译： 一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极 在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开， 包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。
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4.发明授权公开(公告)号：US07233521B1
公开(公告)日：2007-06-19
申请号：US11078761
申请日：2005-03-11
IPC分类号： G11C11/34
CPC分类号： G11C27/005 , G11C11/5621 , G11C16/0441 , G11C16/10
摘要： A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.
摘要翻译： 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间，第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。
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公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。
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公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。
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公开(公告)号：US07075341B1
公开(公告)日：2006-07-11
申请号：US10823455
申请日：2004-04-13
IPC分类号： H03B1/00
CPC分类号： H01L27/0266
摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
摘要翻译： 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。
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公开(公告)号：US07042763B1
公开(公告)日：2006-05-09
申请号：US10895711
申请日：2004-07-08
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C2216/10
摘要： A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.
摘要翻译： 一种选择性地编程非易失性存储单元的方法，其中使用多个编程电压来获得所选择用于编程的单元的存储节点上的期望电压，而未选定单元的存储节点保持不受干扰。
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9.发明授权Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current 有权利用衬底电流的反馈控制的PMOS堆叠栅极存储器单元编程的有效方法公开(公告)号：US06903979B1
公开(公告)日：2005-06-07
申请号：US10664758
申请日：2003-09-17
CPC分类号： G11C16/10
摘要： A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.
摘要翻译： 提供了一种编程PMOS堆叠栅极存储单元的方法，其利用在编程周期期间的注入电流和衬底电流之间的相关性来向存储器单元的控制栅极提供反馈校正，以补偿浮置栅极上的负电位移位 作为其充电时间的结果。
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10.发明申请Gas Detector that Utilizes an Electric Field to Assist in the Collection and Removal of Gas Molecules 有权气体探测器利用电场来辅助气体分子的收集和去除公开(公告)号：US20120060587A1
公开(公告)日：2012-03-15
申请号：US12880464
申请日：2010-09-13
CPC分类号： G01N27/4141
摘要： A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
摘要翻译： 基于半导体的气体检测器增强了气体分子的收集，并且还提供了一种独立的装置，用于通过利用一个或多个电场来将气体分子输送到和远离具有高渗透性的金属材料 气体分子。
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