公开(公告)号：US2401440A

公开(公告)日：1946-06-04

申请号：US43133742

申请日：1942-02-18

Applicant: MONSANTO CHEMICALS

Inventor： THOMAS CHARLES A ,  GENNADY KOSOLAPOFF

IPC: C08B15/06

CPC classification number: C08B15/06

公开(公告)号：US1957253A

公开(公告)日：1934-05-01

申请号：US55824831

申请日：1931-08-20

Applicant: KOPPERS CO INC

Inventor： CONSTANZ EYMANN

IPC: C10K1/08

CPC classification number: C10K1/08

公开(公告)号：US6157831A

公开(公告)日：2000-12-05

申请号：US781261

申请日：1997-01-11

Applicant: James A. Lamb

Inventor： James A. Lamb

IPC: H04W4/16 ,  H04W8/04 ,  H04Q7/20

CPC classification number: H04W8/04 ,  H04W4/16

Abstract: The present invention provides an improved home location register (HLR) that includes an application program for implementing configurable call forwarding bins in a mobile telephone system. According to the invention, a number of call forwarding bins are provided for subscribers. Each forwarding bin must be individually authorized to become available to a subscriber. Furthermore, if a bin is authorized, depending on whether a bin is locked or not, either the cellular carrier or the subscriber can activate the bin and/or modify a forward-to number in the bin. Moreover, a priority list is provided, corresponding to a particular status of the subscriber's cellular phone. (i.e. busy, no answer, etc.) and whether the subscriber is in the home area or a roaming area. The priority list identifies selected bin numbers that the application program needs to check. The bin that has the highest priority on the list and is authorized and activated will be selected. The forward-to number in that bin will be used for call forwarding. If none of the bins in the priority list is authorized and activated, a switch default number is used to redirect incoming calls, so that an announcement will be played to calling parties. Therefore, by using the improved HLR of the invention, more call forwarding bins-can be implemented. Moreover, these bins can be easily configured in desired ways to allow either a cellular carrier or a subscriber to control the use of selected bins. Additionally, in providing call forwarding services, a plurality of bins are checked to find an appropriate forward-to number, thus avoiding sending erroneous messages to calling parties.

Abstract translation: 本发明提供了一种改进的归属位置寄存器（HLR），其包括用于在移动电话系统中实现可配置呼叫转移仓的应用程序。 根据本发明，为用户提供了多个呼叫转移箱。 每个转发箱必须被单独授权才能用于订户。 此外，如果仓被授权，取决于仓是否被锁定，蜂窝运营商或订户可以激活仓和/或修改仓中的前进号码。 此外，提供对应于用户蜂窝电话的特定状态的优先级列表。 （即忙，无应答等）以及用户是否在家庭区域或漫游区域。 优先级列表标识应用程序需要检查的所选bin号码。 将选择列表中具有最高优先级并被授权和激活的bin。 该存储区中的转发号码将用于呼叫转移。 如果优先级列表中的任何一个均未被授权和激活，则使用切换默认号码来重定向来电，以便向主叫方发出通知。 因此，通过使用本发明的改进的HLR，可以实现更多的呼叫转移箱。 此外，这些箱可以容易地以所需的方式配置，以允许蜂窝载体或订户控制所选择的箱的使用。 此外，在提供呼叫转移服务时，检查多个箱以找到适当的转发号码，从而避免向主叫方发送错误消息。

公开(公告)号：US6154831A

公开(公告)日：2000-11-28

申请号：US296356

申请日：1999-04-22

Applicant: John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3824

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The MEU may include a plurality of ALUs, registers partitioned into slots, and a decode unit for decoding an instruction specifying operands from any slot from one register and from a fixed slot of another register as well as different operations to be performed by the ALUs on the operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 MEU可以包括多个ALU，被划分成时隙的寄存器，以及解码单元，用于对来自一个寄存器和另一个寄存器的固定时隙的任何时隙指定操作数的指令进行解码，以及由ALU执行的不同操作 操作数。

公开(公告)号：US6154816A

公开(公告)日：2000-11-28

申请号：US957565

申请日：1997-10-24

Applicant: Simon C. Steely ,  Madhumitra Sharma ,  Stephen R. VanDoren

Inventor： Simon C. Steely ,  Madhumitra Sharma ,  Stephen R. VanDoren

IPC: G06F9/46 ,  G06F12/08 ,  G06F15/167 ,  G06F12/16

CPC classification number: G06F9/52 ,  G06F12/0813 ,  G06F12/0828

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

Abstract translation: 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

公开(公告)号：US6141673A

公开(公告)日：2000-10-31

申请号：US318671

申请日：1999-05-25

Applicant: John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

Inventor： John S. Thayer ,  John Gregory Favor ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F17/14

CPC classification number: G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract translation: 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地中央处理单元（CPU）总线耦合到常规处理器。 MEU采用向量寄存器，向量算术逻辑单元（ALU）和操作数路由单元（ORU），以尽可能少的指令周期执行最大数量的多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US6111753A

公开(公告)日：2000-08-29

申请号：US100699

申请日：1998-06-19

Applicant: James Singer

Inventor： James Singer

IPC: G06F1/18 ,  H05K1/02 ,  H05K1/14 ,  H05K7/20

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/0262 ,  H05K1/141 ,  H05K2201/10196 ,  H05K2201/10689

Abstract: A digital system that includes a main printed circuit board that has a first conductive portion formed thereon is provided. A microprocessor module is coupled to and extends orthogonally from the first conductive portion of the main circuit board. A voltage regulator printed circuit board is coupled to and extends orthogonally from the first conductive portion of the main circuit board adjacent the microprocessor module. The voltage regulator printed circuit board supplies a regulated voltage to the microprocessor module over the first conductive portion.

Abstract translation: 提供一种包括形成有第一导电部分的主印刷电路板的数字系统。 微处理器模块耦合到主电路板的第一导电部分并且从主电路板的第一导电部分垂直延伸。 电压调节器印刷电路板与邻近微处理器模块的主电路板的第一导电部分正交地连接并垂直延伸。 电压调节器印刷电路板在第一导电部分上向微处理器模块提供调节电压。

公开(公告)号：US06084499A

公开(公告)日：2000-07-04

申请号：US777847

申请日：1996-12-31

Applicant: Richard A. Faulk

Inventor： Richard A. Faulk

IPC: H01F3/12 ,  H01F3/14 ,  H01F19/08 ,  H01F17/06 ,  H01F21/08 ,  H01F27/24

CPC classification number: H01F3/12 ,  H01F19/08 ,  H01F3/14

Abstract: A planar-type magnetic structure in which two coils, on two poles of the same core, are separated by an open space which is wide enough and low enough that the air return flux, through the open space, completes the flux circuit for each coil. Thus the coupling coefficient between the two coils is very small, even though they are both mounted on a single continuous core of high-permeability material.

Abstract translation: 一种平面型磁性结构，其中两个线圈在相同的芯的两个极上被开放空间分开，该开放空间足够宽且足够低，使得通过开放空间的空气返回磁通完成每个线圈的磁通电路 。 因此，两个线圈之间的耦合系数非常小，即使它们都安装在高导磁率材料的单个连续芯上。

公开(公告)号：US6055643A

公开(公告)日：2000-04-25

申请号：US937853

申请日：1997-09-25

Applicant: Craig L. Chaiken

Inventor： Craig L. Chaiken

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/445 ,  G06F9/48 ,  G06F11/14

CPC classification number: G06F9/4418 ,  G06F1/3203

Abstract: A method is provided for creating a virtual operating system directed power management event. The method may include executing a prepare-to-sleep routine in a computer system running an Advanced Configuration and Power Interface (ACPI) compliant operating system. The prepare-to-sleep routine may include programming ACPI compliant core logic such as the Intel PIIX4 device to generate an I/O trap system management interrupt (SMI) upon accesses to the ACPI WAK.sub.-- STS register. The prepare-to-sleep routine may also enable non-dedicated event signals, such as legacy IRQs, to serve as resume events. After a resume event, the operating system reads the WAK.sub.-- STS register. Upon access to the WAK.sub.-- STS an SMI is generated. An SMI handler may be executed that determines if the resume event was generated by a wake device. If the resume event was in response to a non-dedicated event signal such as a legacy IRQ, the handler writes to a configuration register in the core logic which causes an unused dedicated event signal to appear as if it was asserted in the ACPI general purpose event register. Upon a subsequent access of the general purpose event register, the operating system will now recognize an ACPI compliant event. Alternatively, the core logic may be modified to include an event status/enable pair for each legacy IRQ.

Abstract translation: 提供了一种用于创建指向电力管理事件的虚拟操作系统的方法。 该方法可以包括在运行高级配置和电源接口（ACPI）兼容操作系统的计算机系统中执行准备睡眠例程。 准备睡眠程序可以包括编程ACPI兼容的核心逻辑，例如Intel PIIX4设备，用于在访问ACPI WAK-STS寄存器时生成I / O陷阱系统管理中断（SMI）。 准备休眠例程还可以使诸如传统IRQ之类的非专用事件信号用作恢复事件。 在恢复事件之后，操作系统读取WAK-STS寄存器。 在访问WAK-STS时，生成SMI。 可以执行SMI处理程序，其确定恢复事件是否由尾流设备产生。 如果恢复事件是响应于诸如传统IRQ的非专用事件信号，则处理程序写入核心逻辑中的配置寄存器，这导致未使用的专用事件信号看起来好像在ACPI通用目的中被断言 事件寄存器。 在随后访问通用事件寄存器时，操作系统现在将识别符合ACPI的事件。 或者，可以修改核心逻辑以包括每个传统IRQ的事件状态/使能对。

公开(公告)号：US6040845A

公开(公告)日：2000-03-21

申请号：US995763

申请日：1997-12-22

Applicant: Maria L. Melo ,  Gregory N. Santos

Inventor： Maria L. Melo ,  Gregory N. Santos

IPC: G06F1/32 ,  G06F13/364 ,  G06F13/14

CPC classification number: G06F1/3253 ,  G06F1/3203 ,  G06F13/364 ,  Y02B60/1235 ,  Y02B60/32

Abstract: A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

Abstract translation: 提供一种计算机，其具有耦合在外围总线和专用图形总线之间的总线接口单元。 图形总线可以通过AGP链接到总线接口单元，而外设总线可以通过PCI链接到总线接口单元。 AGP总线的仲裁可以确定何时授予AGP主控（即图形加速器/控制器）。 在授予主管权之前，AGP目标将降低到总线接口单元内的功耗最小的低功耗状态。 直到AGP主机达到掌握，总线接口单元内的图形目标（核心逻辑和存储器控制器）才能处于运行状态（完全供电）状态。 因此，计算机采用总线接口单元，其可以根据对图形目标的访问而从高功率状态动态切换到低功率状态，反之亦然。