公开(公告)号：US07034737B1

公开(公告)日：2006-04-25

申请号：US11091073

申请日：2005-03-28

Applicant: Kuan-Hsun Huang

Inventor： Kuan-Hsun Huang

IPC: H03M1/12

CPC classification number: H03M1/147

Abstract: A switched capacitor circuit includes an amplifier, a first switched capacitor network, and a second switched capacitor network. Either the first or second switched capacitor network is switched in a sampling configuration or a gain configuration according to connection states of the switches thereof. The amplifier includes a first transistor and a second transistor coupled to the first switched capacitor network, and a third transistor and a fourth transistor coupled to the second switched capacitor network. A first switch is coupled to a first connection point of the first and second transistors, and a second switch is coupled to a second connection point of the third and fourth transistors.

Abstract translation: 开关电容器电路包括放大器，第一开关电容器网络和第二开关电容器网络。 根据其开关的连接状态，第一或第二开关电容器网络以采样配置或增益配置来切换。 放大器包括耦合到第一开关电容器网络的第一晶体管和第二晶体管，以及耦合到第二开关电容器网络的第三晶体管和第四晶体管。 第一开关耦合到第一和第二晶体管的第一连接点，第二开关耦合到第三和第四晶体管的第二连接点。

公开(公告)号：US07034384B2

公开(公告)日：2006-04-25

申请号：US10824267

申请日：2004-04-13

Applicant: Yu-Wen Tsai

Inventor： Yu-Wen Tsai

IPC: H01L23/02

CPC classification number: H01L22/22 ,  H01L23/525 ,  H01L27/118 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit adapted for ECO and FIB debug comprises: a substrate, a spare cell, a top-layer output terminal pad and a top-layer output terminal pad. The spare cell is disposed in substrate and comprises at least one input terminal and at least one output terminal. The top-layer output terminal pad and the top-layer input terminal pad are disposed in a top metal layer. The top metal layer is disposed over the substrate. The top-layer output terminal pad and the top-layer input terminal pad are electrically coupled to the output terminal and input terminal of the spare cell by a via structure, respectively.

Abstract translation: 适用于ECO和FIB调试的集成电路包括：衬底，备用单元，顶层输出端子焊盘和顶层输出端子焊盘。 备用电池设置在衬底中，并且包括至少一个输入端子和至少一个输出端子。 顶层输出端子焊盘和顶层输入端子焊盘设置在顶部金属层中。 顶部金属层设置在基板上。 顶层输出端子焊盘和顶层输入端子焊盘分别通过过孔结构电耦合到备用电池的输出端子和输入端子。

公开(公告)号：US07023244B2

公开(公告)日：2006-04-04

申请号：US10876079

申请日：2004-06-24

Applicant: Chao-Chi Lee ,  Yu-Tong Lin ,  Chih-Fu Chien

Inventor： Chao-Chi Lee ,  Yu-Tong Lin ,  Chih-Fu Chien

IPC: H03K5/22

CPC classification number: H03K17/223

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract translation: 一种电压检测电路，用于检测第一电源的电压电平。 第一晶体管包括耦合到第一栅极的第一栅极，第一源极和第一漏极。 第二晶体管包括耦合到第二栅极的第二栅极，第二源极和第二漏极。 比较器包括第一输入端，耦合到第二漏极的第二输入端和输出端。 第一电阻器耦合在第一输入端子和第一漏极之间。 第二电阻器耦合到第一电源。 第三电阻器耦合在第二电阻器和第一输入端子之间。 第四电阻器耦合在第二电阻器和输入端子之间。 第五电阻器耦合在第一电源和第二电源之间。 电阻器件耦合在第一源和第一电源之间。

公开(公告)号：US06979983B2

公开(公告)日：2005-12-27

申请号：US10833914

申请日：2004-04-28

Applicant: Wen-Cheng Yen ,  Cheng-Chung Chou

Inventor： Wen-Cheng Yen ,  Cheng-Chung Chou

IPC: G05F1/40 ,  G05F1/44 ,  G05F1/56 ,  G11C5/14

CPC classification number: G05F1/56 ,  G11C5/143 ,  G11C5/147

Abstract: A voltage regulator, regulating a supply voltage and outputting a regulated voltage. The voltage regulator comprises a two stage OP which outputs a first voltage and a second voltage according to a reference voltage and a feedback voltage. A NMOS transistor controlled by a voltage detection unit, to receive the second voltage when the detected supply voltage is in a high mode. A PMOS transistor controlled by the voltage detection unit, to receive the first voltage when the detected supply voltage is in a low mode. A feedback circuit for receiving the regulated voltage and outputting the feedback voltage to the two stage OP.

Abstract translation: 电压调节器，调节电源电压并输出调节电压。 电压调节器包括两级OP，其根据参考电压和反馈电压输出第一电压和第二电压。 由电压检测单元控制的NMOS晶体管，当检测到的电源电压处于高模式时接收第二电压。 由所述电压检测单元控制的PMOS晶体管，用于当检测到的电源电压处于低模式时接收第一电压。 用于接收调节电压并将反馈电压输出到两级OP的反馈电路。

公开(公告)号：US06886146B2

公开(公告)日：2005-04-26

申请号：US10248751

申请日：2003-02-14

Applicant: Kuo-Han Hsu

Inventor： Kuo-Han Hsu

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5031

Abstract: A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool. The EDA tool contains a plurality of clocking devices that prevent the timing simulation and authentication software from changing an order of the plurality of clocking devices. The method includes measuring a delay time of the clocking device, and providing a first buffer, which is electrically connected to the clocking device, according to the delay time, wherein the delay time of the first buffer approximates the delay time of the clocking device.

Abstract translation: 一种使用EDA工具（电子设计自动化工具）的时序仿真和认证软件绕过EDA工具中的多个时钟树的方法。 EDA工具包含多个时钟装置，其阻止时序仿真和认证软件改变多个时钟装置的顺序。 该方法包括测量时钟装置的延迟时间，并根据延迟时间提供与时钟装置电连接的第一缓冲器，其中第一缓冲器的延迟时间近似于时钟装置的延迟时间。

公开(公告)号：US5974476A

公开(公告)日：1999-10-26

申请号：US989287

申请日：1997-12-12

Applicant: Tin-Hao Lin ,  Jeng-Huang Wu

Inventor： Tin-Hao Lin ,  Jeng-Huang Wu

IPC: G01R31/3181 ,  H03K19/0185 ,  G06F13/14 ,  G01R31/3187

CPC classification number: H03K19/018585 ,  G01R31/3181

Abstract: An input/output (I/O) device with programmable I/O characteristics is provided for use on an integrated circuit to serve as a communication interface whose input/output characteristics can be set through programmable means to be matched to the external circuitry to which the IC chip is connected for use. This allows the IC chip on which the I/O device is provided to be matched for use with various kinds of external systems. Further, the I/O device can also be provided with a self-control feature that can detect whether the I/O characteristics of the I/O device are matched to the external circuitry and, if not, automatically set the I/O device to the required I/O characteristic. The I/O device can prevent an IC chip from being discarded due to a mismatch in the I/O characteristics with the external circuitry to which the IC chip is connected for use.

Abstract translation: 提供具有可编程I / O特性的输入/输出（I / O）器件用于集成电路，用作通信接口，其输入/输出特性可通过可编程手段设置为与外部电路匹配， IC芯片连接使用。 这允许提供I / O设备的IC芯片与各种外部系统配合使用。 此外，I / O设备还可以具有可以检测I / O设备的I / O特性是否与外部电路匹配的自控功能，如果不是，I / O设备自动设置I / O设备 到所需的I / O特性。 由于I / O特性与IC芯片连接使用的外部电路不匹配，因此I / O设备可以防止IC芯片被丢弃。

公开(公告)号：US11736108B2

公开(公告)日：2023-08-22

申请号：US17974532

申请日：2022-10-27

Applicant: Faraday Technology Corp.

Inventor： Ko-Ching Chao ,  Chih-Hung Wu ,  Po-Wen Hsiao ,  Zhou-Lun Liou

IPC: H03L7/00 ,  G11C11/4076 ,  H03K21/02 ,  H03K19/21

CPC classification number: H03L7/00 ,  G11C11/4076 ,  H03K19/21 ,  H03K21/023

Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

公开(公告)号：US20230029065A1

公开(公告)日：2023-01-26

申请号：US17542531

申请日：2021-12-06

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Bu-Qing Ping

IPC: G06F13/42 ,  H04L69/324

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.

公开(公告)号：US20210365400A1

公开(公告)日：2021-11-25

申请号：US16931373

申请日：2020-07-16

Applicant: Faraday Technology Corp.

Inventor： Ching-Lin Hsu ,  Chang-Hsien Lin

IPC: G06F13/42 ,  G06F13/40

Abstract: An adaptor device including a first interface, a second interface, a negotiation circuit and a type C manager and controller is provided. The first interface is a universal serial bus (USB) 2.0 interface, and the second interface is a type C USB interface. When the first interface receives a first mode swap request, the type C manager and controller transmits a first mode swap signal in a type C format through the second interface according to the first mode swap request; when the second interface receives a second mode swap request, the negotiation circuit transmits a second mode swap signal in a USB 2.0 format through the first interface according to the second mode swap request.

公开(公告)号：US11177932B1

公开(公告)日：2021-11-16

申请号：US17234832

申请日：2021-04-20

Applicant: Faraday Technology Corp.

Inventor： Vinay Suresh Rao ,  Andrew Chao

IPC: H04L7/033 ,  H03M9/00 ,  H03H17/02

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.