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61.发明授权Resistor circuit, interface circuit including resistor circuit, and electronic instrument 有权电阻电路，接口电路包括电阻电路和电子仪器公开(公告)号：US07714607B2
公开(公告)日：2010-05-11
申请号：US11973623
申请日：2007-10-09
申请人： Kiminori Nakajima
发明人： Kiminori Nakajima
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H01C1/16
摘要： A resistor circuit includes n-stage unit circuits, each of which includes a first resistor element provided between first and second terminals, a first disconnection element provided between the second and third terminals, and a second disconnection element and a second resistor element provided in series between the second and fourth terminals. The first terminal of each of the n-stage unit circuits is connected with a first interconnect, the fourth terminal of each of the n-stage unit circuits is connected with a second interconnect, the third terminal of the first-stage unit circuit is connected with a third interconnect, and the third terminal of the mth-stage unit circuit is connected with the second terminal of the (m−1)th-stage unit circuit.
摘要翻译： 一个电阻电路包括n级单元电路，每个单元电路包括设置在第一和第二端子之间的第一电阻元件，设置在第二和第三端子之间的第一断路元件和串联设置的第二断路元件和第二电阻元件 在第二和第四终端之间。 n级单元电路中的每一个的第一端子与第一互连件连接，n级单元电路中的每一个的第四端子与第二互连件连接，第一级单元电路的第三端子连接 并且第m级单元电路的第三端与第（m-1）级单元电路的第二端连接。
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62.发明授权Array of independently-addressable resistors, and method for production thereof 失效可独立寻址的电阻器阵列及其制造方法公开(公告)号：US07642893B2
公开(公告)日：2010-01-05
申请号：US10574257
申请日：2004-10-01
申请人： Adrien Gasse , Guy Parat
发明人： Adrien Gasse , Guy Parat
IPC分类号： H01C13/00
CPC分类号： H01C13/02 , B01L3/5027 , B01L2400/0677 , H01C1/16 , Y10T29/49082
摘要： The arrays of independently-addressable resistors are commonly used to control miniature elements. The invention proposes solving the problem caused by the loss of power dissipated in the addressed resistor by choosing, for this resistor, a material with a negative thermal coefficient resistance, which enables the addressing output of this resistor to be increased.
摘要翻译： 独立寻址电阻器的阵列通常用于控制微型元件。 本发明提出通过为该电阻器选择具有负热系数电阻的材料来解决由寻址电阻器中耗散的功率损耗引起的问题，这使得能够增加该电阻器的寻址输出。
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公开(公告)号：US20090179731A1
公开(公告)日：2009-07-16
申请号：US12355913
申请日：2009-01-19
申请人： Jan Ihle , Werner Kahr , Helmut Poelzl
发明人： Jan Ihle , Werner Kahr , Helmut Poelzl
CPC分类号： H01C7/02 , H01C1/16 , H05B3/34 , H05B2203/005 , H05B2203/009 , H05B2203/017 , Y10T29/49082 , Y10T29/49085
摘要： According to a first preferred embodiment, a resistor arrangement with resistor elements is specified whose first electrodes are conductively connected to each other by means of a flexible, conductive connection element that is curved. The connection element has changes in curvature in the regions arranged between two adjacent resistor elements. According to a second preferred embodiment, a resistor arrangement with resistor elements is specified that are connected to each other by a flexible connection element. The resistor elements each have an arrangement of slot-like recesses.
摘要翻译： 根据第一优选实施例，指定具有电阻元件的电阻器装置，其第一电极通过弯曲的柔性导电连接元件彼此导电连接。 连接元件在布置在两个相邻电阻器元件之间的区域中具有曲率变化。 根据第二优选实施例，规定了具有电阻元件的电阻器组件，其通过柔性连接元件彼此连接。 电阻元件各自具有槽状凹部的布置。
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公开(公告)号：US20080218248A1
公开(公告)日：2008-09-11
申请号：US11740902
申请日：2007-04-26
申请人： Uladzimir KIM
发明人： Uladzimir KIM
IPC分类号： H01H85/00
摘要： A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected. The output terminal is located at the nodes of the third resistor set and the first loading resistor so that the trimming steps provided by the third resistor set and the fourth resistor set are opposite to that of the first resistor set and the second resistor set.
摘要翻译： 公开了二进制双向微调电路。 微调电路包括：具有并联连接的4个电阻器的第一电阻器组和桥接两端的第一熔断器提供一个修整步骤; 具有串联连接的2个电阻器的第二电阻器组和连接两端的第二熔断器提供8个微调步骤; 具有并联连接的2个电阻器的第三电阻器组和桥接两端的第三熔断器提供两个微调步骤; 具有1个电阻器的第四电阻器和桥接两端的第四个熔丝器提供四个修整步骤; 第一负载电阻器; 和第二负载电阻器。 第一电阻器组，第二电阻器组，第一负载电阻器，第三电阻器组，第四电阻器组和第二负载电阻器串联连接。 输出端子位于第三电阻器组和第一负载电阻器的节点处，使得由第三电阻器组和第四电阻器组提供的微调步骤与第一电阻器组和第二电阻器组相反。
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65.发明申请公开(公告)号：US20070247274A1
公开(公告)日：2007-10-25
申请号：US10574257
申请日：2004-10-01
申请人： Adrien Gasse , Guy Parat
发明人： Adrien Gasse , Guy Parat
CPC分类号： H01C13/02 , B01L3/5027 , B01L2400/0677 , H01C1/16 , Y10T29/49082
摘要： The arrays of independently-addressable resistors are commonly used to control miniature elements. The invention proposes solving the problem caused by the loss of power dissipated in the addressed resistor by choosing, for this resistor, a material with a negative thermal coefficient resistance, which enables the addressing output of this resistor to be increased. A production method is also described.
摘要翻译： 独立寻址电阻器的阵列通常用于控制微型元件。 本发明提出通过为该电阻器选择具有负热系数电阻的材料来解决由寻址电阻器中耗散的功率损耗引起的问题，这使得能够增加该电阻器的寻址输出。 还描述了一种制造方法。
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公开(公告)号：US07099140B2
公开(公告)日：2006-08-29
申请号：US10065669
申请日：2002-11-07
IPC分类号： H01G4/228
摘要： A combination run capacitor/positive temperature coefficient resistor/overload (CAP/PTCR/OL) module is described. The cover of the combination housing includes a capacitor compartment and terminal openings for receiving blade terminals of a run capacitor. The terminal openings in the cover align with blade receiving receptacles coupled to the PTCR start circuit. The blade terminals of a run capacitor are inserted into the receptacle openings and into electrical engagement with the blade receiving receptacles. The capacitor is supported and protected by a potting mixture filling the capacitor compartment.
摘要翻译： 描述组合运行电容器/正温度系数电阻器/过载（CAP / PTCR / OL）模块。 组合壳体的盖子包括电容器隔间和用于接收运行电容器的叶片端子的端子开口。 盖中的端子开口与连接到PTCR启动电路的刀片接收插座对齐。 运行电容器的刀片端子插入到插座开口中并与刀片接收插座电接合。 电容器由填充电容器隔间的灌封混合物支撑和保护。
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公开(公告)号：US06963265B2
公开(公告)日：2005-11-08
申请号：US10939085
申请日：2004-09-10
CPC分类号： H01C1/144 , H01C1/16 , H01L23/49816 , H01L2924/0002 , H05K1/167 , H05K3/3436 , H01L2924/00
摘要： A ball grid array resistor network that has a ground plane to reduce noise and improve signal integrity. The ball grid array resistor network includes a substrate having a first and a second surface and vias that extending through the substrate between the first and second surfaces. Resistors are located on the first surface between the vias. Conductors are located over the vias and are electrically connected to ends of the resistors. A cover coat covers the conductors and resistors. A ground plane is located on the second surface. An insulating layer is located over the ground plane. Ball pads are located over the vias. The ball pads are electrically connected to the vias. Solder spheres are attached to the ball pads.
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公开(公告)号：US20050046544A1
公开(公告)日：2005-03-03
申请号：US10939085
申请日：2004-09-10
CPC分类号： H01C1/144 , H01C1/16 , H01L23/49816 , H01L2924/0002 , H05K1/167 , H05K3/3436 , H01L2924/00
摘要： A ball grid array resistor network that has a ground plane to reduce noise and improve signal integrity. The ball grid array resistor network includes a substrate having a first and a second surface and vias that extending through the substrate between the first and second surfaces. Resistors are located on the first surface between the vias. Conductors are located over the vias and are electrically connected to ends of the resistors. A cover coat covers the conductors and resistors. A ground plane is located on the second surface. An insulating layer is located over the ground plane. Ball pads are located over the vias. The ball pads are electrically connected to the vias. Solder spheres are attached to the ball pads.
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公开(公告)号：US20040233606A1
公开(公告)日：2004-11-25
申请号：US10818811
申请日：2004-04-06
发明人： Tatsuya Inoue , Hideaki Tokunaga , Eiichi Uriu , Naotsugu Yoneda , Takeshi Orita
IPC分类号： H02H009/00
摘要： On the surface of a ceramic sinter, at least an external electrode for input, an external electrode for output, and external electrodes for grounding are disposed, and the ceramic sinter includes an inductor electrically connected to the external electrode for input and external electrode for output, and a varistor electrically connected to the external electrode for input and external electrodes for grounding. By connecting the inductor to the signal line of the circuit of an electronic appliance and connecting the varistor between the input side of the signal line and the ground, electrostatic discharge pulses of about 0.5 to 2 nanoseconds can be suppressed efficiently.
摘要翻译： 在陶瓷烧结体的表面上，设置至少一个用于输入的外部电极，用于输出的外部电极和用于接地的外部电极，并且陶瓷烧结体包括电连接到用于输入的外部电极和用于输出的外部电极的电感器 和与外部电极电连接的用于接地的输入和外部电极的变阻器。 通过将电感器连接到电子设备的电路的信号线并将变阻器连接到信号线的输入侧和地之间，可以有效地抑制约0.5至2纳秒的静电放电脉冲。
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公开(公告)号：US20030214383A1
公开(公告)日：2003-11-20
申请号：US10143779
申请日：2002-05-14
发明人： Han-ping Chen
IPC分类号： H01C001/01
摘要： A method and apparatus provides resistor network packages with some of the resistor sub-package positions remain open, which may accommodate different circuit configurations with a common circuit assembly. Also, the present invention provides a packaging method using resistor network packages as connecting and disconnecting mechanisms for the signal lines on the package.
摘要翻译： 一种方法和装置提供电阻器网络封装，其中一些电阻子封装位置保持打开，这可以容纳具有公共电路组件的不同电路配置。 此外，本发明提供一种使用电阻网络封装作为封装上的信号线的连接和断开机构的封装方法。
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