公开(公告)号：US08650633B2

公开(公告)日：2014-02-11

申请号：US13250529

申请日：2011-09-30

Applicant: Love Kothari ,  Paul Chou

Inventor： Love Kothari ,  Paul Chou

IPC: G06F21/00

CPC classification number: H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

Abstract: An integrated circuit is disclosed that can be included in a host electronic device that can be commonly manufactured, where the integrated circuit can be designated (“locked”) for a specific manufacturer, thereby substantially reducing the likelihood that a third party will be able to successfully clone a host electronic device manufactured by the specific manufacturer and/or swap the chip containing the integrated circuit for one having more enabled features. The integrated circuit includes an ID module that can be programmed after fabrication. Components within the integrated circuit designate manufacturer-specific configurations (e.g., address mapping, pin routing and/or vital function releasing) based on the programmed manufacturer ID. As a result, once the integrated circuit has been programmed with the manufacturer ID, the integrated circuit will function correctly only within a host device manufactured by the manufacturer associated with the programmed manufacturer ID.

Abstract translation: 公开了一种集成电路，其可以被包括在可以通常制造的主机电子设备中，其中可以为特定制造商指定（“锁定”）集成电路，从而显着降低第三方将能够 成功克隆由特定制造商制造的主机电子设备和/或将包含集成电路的芯片交换为具有更多启用特征的芯片。 集成电路包括可在制造后编程的ID模块。 集成电路中的组件基于编程的制造商ID指定制造商特定的配置（例如，地址映射，引脚布线和/或重要功能释放）。 因此，一旦集成电路已经用制造商ID编程，集成电路将仅在制造商制造的与编程的制造商ID相关联的主机设备中正常工作。

公开(公告)号：US20140002166A1

公开(公告)日：2014-01-02

申请号：US13551835

申请日：2012-07-18

Applicant: Ekram H. Bhuiyan ,  Steve X. Chi

Inventor： Ekram H. Bhuiyan ,  Steve X. Chi

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H03K2005/00143

Abstract: Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.

Abstract translation: 描述延迟电路，其延迟在电源电压和/或温度的变化的期望范围内基本上保持恒定。

公开(公告)号：US08618857B2

公开(公告)日：2013-12-31

申请号：US13431595

申请日：2012-03-27

Applicant: Yan Dong ,  Peng Xu

Inventor： Yan Dong ,  Peng Xu

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H02M3/1588 ,  H03K17/284 ,  Y02B70/1466

Abstract: The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.

Abstract translation: 本发明的实施例公开了延迟电路。 所述延迟电路包括反相器，负载电容器和第一电压钳位模块，其中所述第一电压钳位模块产生电压降，所述电压降配置为当所述电源电压降低时延长所述延迟电路的传播延迟时间。 电源相关延迟电路在低电源电压下的输入信号上升沿或下降沿的高电源电压可能具有大得多的传播延迟时间。

公开(公告)号：US20130342256A1

公开(公告)日：2013-12-26

申请号：US13527908

申请日：2012-06-20

Applicant: Sameer Wadhwa ,  Marzio Pedrali-Noy

Inventor： Sameer Wadhwa ,  Marzio Pedrali-Noy

IPC: H03K5/159

CPC classification number: H03K5/159 ,  H03K3/356104 ,  H03K5/133

Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.

Abstract translation: 公开了与温度无关的延迟元件和振荡器。 在一种设计中，装置包括至少一个延迟元件，偏置电路和电流源。 延迟元件从电流源接收充电电流并提供取决于充电电流的延迟。 每个延迟元件可以是当前饥饿的延迟元件。 延迟元件可以串联耦合以实现延迟线或在环路中实现振荡器。 偏置电路基于至少一个延迟元件的至少一个参数（例如，开关阈值电压）的功能来控制充电电流的产生，以便减少随温度延迟的变化。 电流源为延迟元件提供充电电流，并由偏置电路控制。

公开(公告)号：US20130342255A1

公开(公告)日：2013-12-26

申请号：US14014725

申请日：2013-08-30

Applicant: FUJITSU LIMITED

Inventor： Yoshihiko SATSUKAWA

IPC: H03K5/14

CPC classification number: H03K5/14 ,  H03K5/13 ,  H03K5/133 ,  H03K19/0016

Abstract: A signal delay device includes a delay unit including delay parts connected to one another in series and generating a delay signal; a selection unit to output the delay signal and including selectors connected to one another in series and outputting the delay signal, each selector receiving an output of one of the delay parts, being supplied with an output of former selector, and outputting the output of the delay part or the output of the former selector, based on a selection signal; a register unit holding delay setting data to set an amount of delay of the signal delay device; and a selection signal generator generating a selection signal indicating one of the selectors selecting an output of one of the delay parts based on the delay setting data and outputting the generated selection signal to the selection unit.

Abstract translation: 信号延迟装置包括延迟单元，该延迟单元包括彼此串联连接并产生延迟信号的延迟部分; 选择单元，输出所述延迟信号并且包括彼此串联连接的选择器，并输出所述延迟信号，每个选择器接收所述延迟部分中的一个的输出，被提供有前一选择器的输出，并输出所述延迟信号的输出 延迟部分或前一个选择器的输出; 寄存器单元，保持延迟设置数据以设置信号延迟装置的延迟量; 以及选择信号发生器，其基于所述延迟设置数据产生指示所述选择器之一选择所述延迟部分的输出的选择信号，并将所生成的选择信号输出到所述选择单元。

公开(公告)号：US08601427B2

公开(公告)日：2013-12-03

申请号：US13362414

申请日：2012-01-31

Applicant: Masakuni Kawagoe

Inventor： Masakuni Kawagoe

IPC: G06F17/50

CPC classification number: H03L7/00 ,  G06F17/5059 ,  H03K3/0375 ,  H03K5/133

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract translation: 半导体集成电路包括连接在数据位源和锁存电路的数据输入端之间的延迟电路。 延迟电路包括第一延迟部分，该第一延迟部分通过连接对应于时钟信号源和锁存电路数据输入之间的时钟信号路径中包括的多个逻辑器件的串联逻辑器件而形成。 延迟电路还包括具有等于对应于时钟信号路径的布线长度的互连延迟时间的延迟时间的第二延迟部分。

公开(公告)号：US20130314140A1

公开(公告)日：2013-11-28

申请号：US13953500

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Feng Lin

IPC: H03H11/26

CPC classification number: H03K5/133 ,  H03H11/26 ,  H03H11/265 ,  H03K5/131

Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

Abstract translation: 描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。 描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。 偏置信号可以部分地基于模拟延迟线的操作频率。

公开(公告)号：US08570084B2

公开(公告)日：2013-10-29

申请号：US13610526

申请日：2012-09-11

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03L7/0814

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract translation: 公开了用于校正占空比失真的占空比校正电路，时钟分配网络和方法，包括用于校正从时钟分配网络提供的差分输出时钟信号的占空比失真的方法和装置。 在一种这样的方法中，从差分输入时钟信号产生单端时钟信号，以便在时钟分配网络上进行分配，从而生成差分输出时钟信号。 模型延迟路径的延迟与时钟分配网络的传播延迟相匹配，并且调整单端时钟信号以补偿占空比失真。

公开(公告)号：US08533252B2

公开(公告)日：2013-09-10

申请号：US12434690

申请日：2009-05-04

Applicant: Chia-Liang Lin ,  Hsin-Che Chiang

Inventor： Chia-Liang Lin ,  Hsin-Che Chiang

IPC: G06G7/02

CPC classification number: H03K5/133 ,  H03K2005/00208

Abstract: A broad-band active delay line includes a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell includes a feedback loop and a feedforward path to achieve a high bandwidth.

Abstract translation: 宽带有源延迟线包括以级联拓扑配置的多个宽带有源延迟单元。 每个宽带有源延迟单元包括一个反馈回路和一个实现高带宽的前馈路径。

公开(公告)号：US08504867B2

公开(公告)日：2013-08-06

申请号：US12892854

申请日：2010-09-28

Applicant: Eric B Kushnick

Inventor： Eric B Kushnick

IPC: G06F1/24

CPC classification number: H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058 ,  H03K2005/00097 ,  H03L7/0812

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.