公开(公告)号：US4523322A

公开(公告)日：1985-06-11

申请号：US452565

申请日：1982-12-23

Applicant: Jean-Claude Abbiate

Inventor： Jean-Claude Abbiate

IPC: H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L7/02

CPC classification number: H04L7/0331 ,  H03L7/0993

Abstract: An interface device for synchronizing an internally clocked modem and data terminal equipment (DTE) provided with their own clock circuits, each of said own terminal clock circuit providing an external clock signal (RC Ext). The interface includes a PLO generating a recovered clock signal (XCO). At a moment defined by a request to send signal the phases of XCO and RC Ext are compared with each other and a switched clock signal SWC oscillating at a fast rate for a time interval corresponding to the phase delay between RC Ext and XCO and subsequently oscillating at a slow rate, is generated. The signal SWC is used for shifting RC Ext and terminal provided data RD Ext into shift registers respectively. The shifted RC Ext is used for controlling the adjustment of the interface PLO.

Abstract translation: 一种用于使内部计时的调制解调器与设置有它们自己的时钟电路的数据终端设备（DTE）同步的接口设备，每个所述自己的终端时钟电路提供外部时钟信号（RC Ext）。 接口包括产生恢复时钟信号（XCO）的PLO。 在由发送信号的请求定义的时刻，将XCO和RC Ext的相位相互比较，并且交换时钟信号SWC以快速速率振荡一段对应于RC Ext和XCO之间的相位延迟并随后振荡的时间间隔 以较慢的速度生成。 信号SWC用于将RC Ext和端子提供的数据RD Ext分别移位到移位寄存器中。 移位的RC Ext用于控制接口PLO的调整。

公开(公告)号：US4445224A

公开(公告)日：1984-04-24

申请号：US327730

申请日：1981-12-04

Applicant: Kuninosuke Ihira ,  Shigeyuki Unagami ,  Takashi Kaku

Inventor： Kuninosuke Ihira ,  Shigeyuki Unagami ,  Takashi Kaku

IPC: H04L7/033 ,  H03L7/099 ,  H04L7/02 ,  H04L7/027 ,  H04L27/227 ,  H03L7/06

CPC classification number: H04L7/027 ,  H03L7/0993 ,  H04L27/2272 ,  H04L7/02

Abstract: The present invention relates to a digital phase locked loop circuit, particularly to a circuit which realizes accurately digital phase locked loop pull-in operation at a high speed with a simplified circuit structure.In the present invention, in order to obtain a phase difference between a single frequency signal and the digital phase locked loop clock signal which is obtained by dividing a specified frequency signal with a dividing counter, the phase difference is obtained in accordance with the signs, absolute values and amplitude ratio of two adjacent sample values. The sample values of said single frequency signal are taken at two points based on said digital phase locked loop clock signal corresponding to a phase difference of .pi./2 radians of said single frequency signal. A fast pull-in of the digital phase locked loop is realized by setting a value corresponding to the obtained phase difference into a dividing counter.

Abstract translation: 数字锁相环电路技术领域本发明涉及一种数字锁相环电路，特别涉及一种以简化的电路结构实现高速数字锁相环引入操作的电路。 在本发明中，为了获得单分频信号与通过用分频计数器分割指定频率信号而获得的数字锁相环时钟信号之间的相位差，根据符号获得相位差， 两个相邻样本值的绝对值和幅度比。 基于对应于所述单频信号的π/ 2弧度的相位差的所述数字锁相环时钟信号，在两个点处获取所述单频信号的采样值。 通过将与获得的相位差对应的值设置为分频计数器来实现数字锁相环的快速拉入。

公开(公告)号：US4424497A

公开(公告)日：1984-01-03

申请号：US259020

申请日：1981-04-30

Applicant: Michael W. Fellinger

Inventor： Michael W. Fellinger

IPC: H04L25/49 ,  G11B20/14 ,  H03L7/06 ,  H03L7/099 ,  H03M5/04 ,  H04L7/033 ,  H04L27/152 ,  H03L7/08 ,  H03D3/18

CPC classification number: H04L7/0331 ,  H03L7/06 ,  H03L7/0993

Abstract: In a system having a frequency encoded data stream and a source of clock signals phase locked to the data stream, for subsequent demodulation of the data stream, the clock source is at a frequency that is a multiple of the nominal frequency for demodulating, and a counter is employed to divide the clock. The counter is controlled by the output of a phase comparator, to control the addition to and inhibiting of counting of the counter. The control circuit controls the counter in a non-linear relationship with respect to the phase error, and has a memory function for storing previous states of the counter, to permit repetitive correction for small errors in the same manner. The phase comparator and control are preferably a programmed logic array.

Abstract translation: 在具有频率编码数据流和锁相到数据流的时钟信号源的系统中，为了数据流的后续解调，时钟源的频率是用于解调的额定频率的倍数，并且 计数器用于分时钟。 计数器由相位比较器的输出控制，以控制对计数器的计数的增加和禁止。 控制电路相对于相位误差以非线性关系控制计数器，并且具有用于存储计数器的先前状态的存储功能，以允许以相同的方式对小错误进行重复校正。 相位比较器和控制优选地是编程逻辑阵列。

公开(公告)号：US4031317A

公开(公告)日：1977-06-21

申请号：US657425

申请日：1976-02-12

Applicant: Herbert D. McClain ,  Bipin D. Parikh ,  John K. Burkey

Inventor： Herbert D. McClain ,  Bipin D. Parikh ,  John K. Burkey

IPC: H03L7/06 ,  G06F13/00 ,  H03L7/099 ,  H04L7/033 ,  H04L7/02

CPC classification number: H03L7/0993 ,  H04L7/0331

Abstract: A digital timing recovery circuit is disclosed for synchronously transmitting digitally encoded data in a multiterminal configuration between a data processor and a plurality of data terminals associated therewith. Phase shifted synchronous data from the data processor is continuously compared with a newly generated synchronous clock generated at a repeater interposed along the communication line for minimization of the time differential between the retiming clock and the transmitted data. The data transitions enable a digitally implemented one-shot, which generates pulses, the leading edges of which pulses enable a difference counter, while the leading edges of the retiming clock pulses disable the counter. The difference counter output is sampled in a digital phase locked loop to derive the number of cycles of a stable oscillator which occur between the two aforementioned leading edges of the generated pulses. A difference of less than a predetermined count such as two, results in no correction of the retiming clock, a difference count greater than such predetermined amount, such as a count of three through seven, advances the clock by adding a pulse to the retiming clock, and a difference of more than a predetermined number of counts, such as eight, retards the clock by subtracting a pulse from the retiming clock. Thus, continuous digital adjustment of the synchronous clock is provided to maintain the counter difference below a predetermined count, such as two, which serves to resynchronize bit-shifted data with the retiming clock for retransmission into the communications channel.

Abstract translation: 公开了一种数字定时恢复电路，用于在数据处理器和与其相关联的多个数据终端之间以多终端配置同步传输数字编码数据。 连续地将来自数据处理器的相移同步数据与沿着通信线插入的中继器产生的新生成的同步时钟进行比较，以使重新定时时钟与发送数据之间的时间差最小化。 数据转换使得能够产生数字实现的单触发脉冲，其产生脉冲，其脉冲的前沿使能差分计数器，而重新定时时钟脉冲的前沿禁止计数器。 差分计数器输出在数字锁相环中被采样，以得出在产生的脉冲的两个前述前沿之间出现的稳定振荡器的周期数。 小于预定计数（诸如2）之间的差导致重新定时时钟的校正不会产生大于这样的预定量的差分计数，例如三到七的计数，通过向重新定时时钟添加脉冲来提前时钟 ，并且超过预定数量的计数（例如8）的差通过从重新定时钟减去脉冲来延迟时钟。 因此，提供同步时钟的连续数字调整以将计数器差异维持在预定计数（例如2）以下，其用于将位移数据与重新定时时钟重新同步以重新传输到通信信道中。

公开(公告)号：US4019153A

公开(公告)日：1977-04-19

申请号：US512733

申请日：1974-10-07

Applicant: Duncan B. Cox, Jr. ,  William H. Lee

Inventor： Duncan B. Cox, Jr. ,  William H. Lee

IPC: H03H17/02 ,  H03L7/07 ,  H03L7/099 ,  H04L7/033 ,  H03B3/04

CPC classification number: H03H17/02 ,  H03L7/07 ,  H03L7/0993 ,  H04L7/0331

Abstract: A phase processing system which includes at least one digital phase-locked loop wherein the phase of the input signal to the loop is compared with the phase of the loop output signal to produce a pulse-width modulated phase error signal. The error signal is digitally integrated, as by a counting means which cyclically counts the pulse widths thereof and provides a first control signal when the count reaches a first value and a second control signal when the count reaches a second value. The control signals are used to control the pulse rate of a clock signal to produce an intermediate clock signal such that when the first control signal is present a pulse is added thereto and when the second control signal is present a pulse is deleted therefrom. The intermediate clock signal is then fed to a feedback divider counting means which provides the loop output signal.

Abstract translation: 一种相位处理系统，其包括至少一个数字锁相环，其中将所述环路的输入信号的相位与所述环路输出信号的相位进行比较，以产生脉宽调制的相位误差信号。 误差信号通过对计数其脉冲宽度进行周期性计数的计数装置进行数字积分，当计数达到第一值时提供第一控制信号，当计数达到第二值时提供第二控制信号。 控制信号用于控制时钟信号的脉冲频率以产生中间时钟信号，使得当存在第一控制信号时，向其添加脉冲，并且当存在第二控制信号时，从其中删除脉冲。 然后将中间时钟信号馈送到提供环路输出信号的反馈分频器计数装置。

公开(公告)号：US3919647A

公开(公告)日：1975-11-11

申请号：US51881474

申请日：1974-10-29

Applicant: SIEMENS AG

Inventor： HAASS ADOLF

IPC: H03L7/099 ,  H04L7/033 ,  H04B1/02

CPC classification number: H03L7/0992 ,  H03L7/0993 ,  H04L7/033

Abstract: The invention relates to a circuit arrangement for adjusting the phase state of a timing signal. A divider signal is conducted via a first input of a frequency alteration stage to a frequency divider from the output of which the timing signal is emitted. A binary signal is also provided which for example can be employed to transmit data in the frame of a bit pattern from a transmitting station to a receiving station, the receiving station being synchronized using the timing signal. In dependence upon the phase states of the timing signal and the binary signal, as applied to a discriminator, a discriminator signal is obtained and is conducted to a second input of the frequency alteration stage. Also a third input of the frequency alteration stage is supplied with a signal which indicates whether and how many pulse edges of the divider signal are to be suppressed or pulse edges are to be added to the divider signal.

Abstract translation: 本发明涉及一种用于调整定时信号的相位状态的电路装置。 分频器信号经由频率改变级的第一输入端从定时信号的输出被发送到分频器。 还提供了一种二进制信号，例如可以采用这种二进制信号来从发送站到接收站的位模式帧中发送数据，接收站使用定时信号进行同步。 根据定时信号和二进制信号的相位状态，当应用于鉴频器时，获得鉴频信号，并将其传导到频率变换级的第二输入端。 另外，频率改变级的第三输入端被提供有一个信号，该信号指示除法器信号的脉冲边缘是否被消除，或者将脉冲边缘加到除法器信号上。

公开(公告)号：US3671776A

公开(公告)日：1972-06-20

申请号：US3671776D

申请日：1970-05-01

Applicant: XEROX CORP

Inventor： HOUSTON ROBERT D

IPC: H03L7/099 ,  H04L7/033 ,  H03K5/00 ,  H03K17/00

CPC classification number: H04L7/0331 ,  H03L7/0993

Abstract: A digital signal synchronizing system wherein a locally generated timing signal is compared with received binary data. If the timing signal lags the bit rate of the binary data, pulses are added to the timing signal and if the timing signal leads the binary data, pulses are deleted from the timing signal. Means are provided for controlling the bandwidth of the system and the system, in addition, has a phase versus frequency response which is substantially constant over the range of operating frequencies.

Abstract translation: 一种数字信号同步系统，其中将本地生成的定时信号与接收的二进制数据进行比较。 如果定时信号滞后于二进制数据的比特率，则将脉冲加到定时信号上，如果定时信号导致二进制数据，则从定时信号中删除脉冲。 提供了用于控制系统和系统的带宽的装置，此外，具有在工作频率范围上基本恒定的相位对频率响应。