-
公开(公告)号：US20050270940A1
公开(公告)日：2005-12-08
申请号：US11143288
申请日：2005-06-02
Applicant: Kuang-Yu Yen
Inventor： Kuang-Yu Yen
Abstract: The statistical circuit includes a pulse-width measuring unit, serially coupling delay units, a logical circuit and counters. The pulse-width measuring unit is for receiving a sampling signal and generating a pulse-width signal. A pulse occurs on the pulse-width signal as the sampling signal has status change. The delay units include a first delay unit for receiving the pulse-width signal and outputting delay signals according to the trigger of a reference clock. The output of the first delay unit is used as a reset signal. The logic circuit is for receiving the pulse-width signal and the reset signal and generating a counting signal. The counting signal is enabled for a period of time as a pulse occurs on the pulse-width signal. The counters are respectively for receiving the delay signals and counting the number of the received delay signals in a first status as the trigger signal is enabled.
Abstract translation: 统计电路包括脉冲宽度测量单元，串联耦合延迟单元，逻辑电路和计数器。 脉冲宽度测量单元用于接收采样信号并产生脉冲宽度信号。 当采样信号具有状态变化时，脉冲宽度信号发生脉冲。 延迟单元包括用于接收脉冲宽度信号并根据参考时钟的触发输出延迟信号的第一延迟单元。 第一延迟单元的输出用作复位信号。 逻辑电路用于接收脉冲宽度信号和复位信号并产生计数信号。 当脉冲发生在脉冲宽度信号时，计数信号使能一段时间。 这些计数器分别用于接收延迟信号并且在触发信号被使能时以第一状态对接收的延迟信号的数量进行计数。
-
62.发明授权Voltage built-in real-time digital non-linearity measurement device and method for analog to digital converters 有权电压内置实时数字非线性测量装置和方法用于模数转换器公开(公告)号：US06943712B1
公开(公告)日：2005-09-13
申请号：US10795907
申请日：2004-03-08
Applicant: Pierte Roo , Francis Campana , William Lo
Inventor： Pierte Roo , Francis Campana , William Lo
IPC: H03M1/10
Abstract: A nonlinearity detection system and method for an analog to digital converter (ADC) includes a triangular wave generator that generates a triangular wave that is output to the ADC. A differentiator module communicates with the ADC and generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.
Abstract translation: 用于模数转换器（ADC）的非线性检测系统和方法包括三角波发生器，其产生输出到ADC的三角波。 微分器模块与ADC进行通信，并产生基于ADC输出和ADC延迟输出的输出信号。 非线性检测模块检测微分器模块的输出信号中的斜率不连续性。
-
63.发明申请Diagnostic compiler for pipeline analog-to-digital converter, method of compiling and test system employing the same 有权用于管道模数转换器的诊断编译器，采用该方法的编译和测试系统公开(公告)号：US20050071829A1
公开(公告)日：2005-03-31
申请号：US10672609
申请日：2003-09-26
Applicant: Patrick Bohan
Inventor： Patrick Bohan
Abstract: The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.
Abstract translation: 本发明涉及一种与具有对应于其阶段的代码序列的流水线模数转换器（ADC）一起使用的诊断编译器。 在一个实施例中，诊断编译器包括被配置为确定代码序列的转换位置的转换定位器。 诊断编译器还包括耦合到转换定位器的特征指示符，并且被配置为基于转换位置提供ADC的至少一个特性。
-
公开(公告)号：US06798185B2
公开(公告)日：2004-09-28
申请号：US10185811
申请日：2002-06-28
Applicant: Steven J. Tanghe , Sharon L. Von Bruns
Inventor： Steven J. Tanghe , Sharon L. Von Bruns
IPC: G01R1314
Abstract: A method and apparatus for testing ADC circuitry. The method and apparatus detects infrequently occurring errors by providing a series of waveforms to the ADC that have different amplitude, frequency, or voltage offset from one another. The outputs of the ADC for the waveforms are then analyzed for timing related errors.
Abstract translation: 用于测试ADC电路的方法和装置。 该方法和装置通过向ADC提供彼此具有不同幅度，频率或电压偏移的一系列波形来检测不常发生的错误。 然后分析用于波形的ADC的输出与时序相关的误差。
-
65.发明授权公开(公告)号：US06693570B2
公开(公告)日：2004-02-17
申请号：US10283097
申请日：2002-10-30
Applicant: Shinsuke Ohnishi , Daisuke Takagi
Inventor： Shinsuke Ohnishi , Daisuke Takagi
IPC: H03M110
Abstract: Digital-to-analog (DA) conversion circuitry with a simplified testing circuit includes a DA converter to which test data, initially “0”, may be applied. The DA converter feeds an analog voltage corresponding to the test data to a voltage holding circuit. Subsequently the test data is incremented to “1” and then converted to a corresponding analog voltage by the DA converter. A comparator compares the analog voltage corresponding to the test data “1” with the previous analog voltage held in the voltage holding circuit and corresponding to the test data “0”. When the test data is sequentially incremented by 1 (one) at intervals, the voltage output from the DA converter is higher than the voltage held in the voltage holding circuit while the DA converter operates normally. The function of the DA converter can be easily, rapidly tested by monitoring the output of the comparator.
Abstract translation: 具有简化测试电路的数模（DA）转换电路包括DA转换器，可以应用测试数据，最初为“0”。 DA转换器将对应于测试数据的模拟电压馈送到电压保持电路。 随后，测试数据增加到“1”，然后由DA转换器转换成相应的模拟电压。 比较器将对应于测试数据“1”的模拟电压与保持在电压保持电路中的先前的模拟电压进行比较，并对应于测试数据“0”。 当测试数据间隔地顺序增加1（1）时，DA转换器输出的电压高于保持在电压保持电路中的电压，而DA转换器正常工作。 DA转换器的功能可以通过监视比较器的输出来轻松快速地测试。
-
Patent Agency Ranking
公开(公告)号：US20040000899A1
公开(公告)日：2004-01-01
申请号：US10185811
申请日：2002-06-28
Applicant: International Business Machines Corporation
Inventor： Steven J. Tanghe , Sharon L. Von Bruns
IPC: G01R013/14
Abstract: A method and apparatus for testing ADC circuitry. The method and apparatus detects infrequently occurring errors by providing a series of waveforms to the ADC that have different amplitude, frequency, or voltage offset from one another. The outputs of the ADC for the waveforms are then analyzed for timing related errors.
-
67.发明授权Circuit configuration for testing and A/D converter for applications that are critical in terms of safety 失效用于测试和A / D转换器的电路配置，用于在安全性方面至关重要的应用公开(公告)号：US06518900B1
公开(公告)日：2003-02-11
申请号：US09857282
申请日：2001-09-06
Applicant: Peter Oehler , Wolfgang Fey
Inventor： Peter Oehler , Wolfgang Fey
IPC: H03M110
Abstract: The present invention relates to a circuit configuration with an A/D converter, especially for applications that are critical in terms of safety, which is especially characterized by a ramp signal generator for generating a ramp voltage that is delivered to the input of the A/D converter, and a test circuit for activating a test cycle which comprises a first run of the ramp, by which a reference measurement of the ramp signal generator is carried out for compensating component tolerances, and comprises a second run of the ramp where an error signal is output when the value that is calculated for a transmission characteristic of the A/D converter lies outside a predetermined tolerance range of the measured value of the transmission characteristic.
Abstract translation: 本发明涉及一种具有A / D转换器的电路配置，特别是对于在安全性方面至关重要的应用中，其特征在于用于产生斜坡电压的斜坡信号发生器，该斜坡信号发生器被传送到A / D转换器和用于激活测试周期的测试电路，其包括斜坡的第一次运行，通过该测试循环执行斜坡信号发生器的参考测量以补偿部件公差，并且包括斜坡的第二次运行，其中错误 当对于A / D转换器的传输特性计算的值位于传输特性的测量值的预定公差范围之外时，输出信号。
-
68.发明授权公开(公告)号：US06404375B1
公开(公告)日：2002-06-11
申请号：US09393091
申请日：1999-09-09
Applicant: Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
Inventor： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC: H03M112
CPC classification number: H03M1/1042 , H03M1/0692 , H03M1/109 , H03M1/46
Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
Abstract translation: 用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。 计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。 此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。
-
69.发明授权Decoder testing apparatus and methods that simultaneously apply the same multibit input data to multiple decoders 失效解码器测试装置和方法同时将相同的多位输入数据应用于多个解码器公开(公告)号：US06384754B1
公开(公告)日：2002-05-07
申请号：US09103122
申请日：1998-06-23
Applicant: Sang-ho Park
Inventor： Sang-ho Park
IPC: H03M110
CPC classification number: H03M1/109 , H03M1/66 , Y10S345/904
Abstract: A decoding system includes a plurality of decoders, a respective one of which is responsive to respective multibit input data, to decode the respective multibit input data and produce a respective output level corresponding to the respective multibit input data. The same multibit input data is simultaneously applied to the plurality of decoders, in response to a test mode signal. Different multibit input data is then simultaneously applied to the plurality of decoders, so that all of the output levels of the decoders can be tested. The output levels from the plurality of decoders that result from the same multibit input data that is supplied to the plurality of decoders is detected. The detected output levels from the plurality of decoders that result from the same multibit input data that is applied to the plurality of decoders is compared to expected output levels in order to test the decoders.
Abstract translation: 解码系统包括多个解码器，其中的一个解码器响应于相应的多位输入数据，对相应的多位输入数据进行解码，并产生对应于相应多位输入数据的相应输出电平。 响应于测试模式信号，相同的多位输入数据同时应用于多个解码器。 然后将不同的多位输入数据同时施加到多个解码器，使得可以测试解码器的所有输出电平。 检测从提供给多个解码器的同一多位输入数据得到的来自多个解码器的输出电平。 将来自应用于多个解码器的相同多位输入数据产生的来自多个解码器的检测输出电平与预期输出电平进行比较，以测试解码器。
-
公开(公告)号：US3154738A
公开(公告)日：1964-10-27
申请号：US15137361
申请日：1961-11-09
Applicant: BELL TELEPHONE LABOR INC
Inventor： GREENE JR PATRICK J , WILLIAMS OWEN L , YAEGER ROBERT E
-
-
-
-
-
-
-
-
-
Search Results
209
records
(took 0.039 seconds)
