公开(公告)号：US06385236B1

公开(公告)日：2002-05-07

申请号：US09166304

申请日：1998-10-05

Applicant: Dao-Long Chen

Inventor： Dao-Long Chen

IPC: H04B1700

CPC classification number: H04L1/243 ,  H04B17/10 ,  H04B17/20

Abstract: A circuit and method for testing a transceiver. The circuit includes a bit pattern generator connected to the transceiver such that the bit pattern generator can communicate a serial data stream to a receiver portion of the transceiver. The circuit also includes a bit pattern checker connected to the transceiver such that a transmitter portion of the transceiver can communicate a serial data stream to the bit pattern checker. The transceiver is configured such that the receiver portion of the transceiver is communicatingly looped back to the transmitter portion of the transceiver such that a data stream can be communicated from the receiver portion of the transceiver to the transmitter portion of the transceiver. Desirably, a loopback circuit in connected to the transceiver and includes fixed bit pattern means for communicating at least one fixed bit pattern to the transmitter portion of the transceiver. The loopback circuit is configured such that the FIFO component receives a set of bits from the receiver portion of the transceiver and at least one of the bits in the set is replaced by the fixed bit pattern before being communicated to the transmitter portion of the receiver.

Abstract translation: 用于测试收发器的电路和方法。 电路包括连接到收发器的位模式发生器，使得位模式发生器可将串行数据流传送到收发器的接收器部分。 电路还包括连接到收发器的位模式检查器，使得收发器的发送器部分可以将串行数据流传送到位模式检查器。 收发器被配置为使得收发器的接收器部分被通信地环回到收发器的发射器部分，使得数据流可以从收发器的接收机部分传送到收发器的发射器部分。 期望地，连接到收发器的环回电路并且包括用于将至少一个固定位模式传送到收发器的发送器部分的固定位模式装置。 环回电路被配置为使得FIFO组件从收发器的接收器部分接收一组位，并且在被传送到接收器的发射器部分之前，该组中的位中的至少一个被固定位模式替换。

公开(公告)号：US20020009181A1

公开(公告)日：2002-01-24

申请号：US09772961

申请日：2001-01-31

Inventor： Joe Teixeria

IPC: H04M001/24 ,  H04M003/22

CPC classification number: H04Q1/145 ,  H04L1/243 ,  H04M3/2209 ,  H04M3/30 ,  H04M11/062 ,  H04M2207/203 ,  H04Q1/147

Abstract: A cross connect physical layer switching system is integrated into a central office and facilitates delivering data services, such as digital subscriber line (DSL) service, to subscribers over a shared data and voice line. The cross connect physical layer switching system may be placed between a splitter and the shared line to allow a remote test unit to be controllably connected to the shared line to permit testing of the shared line by a competitive local exchange carrier (CLEC). By placing the physical layer switching system in the CO, both the CLEC and the incumbent local exchange carrier (ILEC) have fill access to the test head (RTU) and full spectrum testing of the line. This allows test access to continue to be done remotely as in an unshared line environment.

Abstract translation: 交叉连接物理层交换系统被集成到中心局中，并且通过共享数据和语音线路向用户提供诸如数字用户线（DSL）服务的数据服务。 交叉连接物理层交换系统可以放置在分路器和共享线路之间，以允许远程测试单元可控地连接到共享线路，以允许竞争性本地交换运营商（CLEC）对共享线路进行测试。 通过将物理层交换系统放置在CO中，CLEC和现有的本地交换运营商（ILEC）都可以访问测试头（RTU）和线路的全频谱测试。 这允许测试访问在非共享线路环境中继续远程完成。

公开(公告)号：US6028845A

公开(公告)日：2000-02-22

申请号：US754183

申请日：1996-11-22

Applicant: Atsuo Serikawa ,  Yasuhiro Saito ,  Yuji Maeda ,  Satoshi Kasuya

Inventor： Atsuo Serikawa ,  Yasuhiro Saito ,  Yuji Maeda ,  Satoshi Kasuya

IPC: H04J3/14 ,  G08C15/00 ,  H04B3/46 ,  H04B17/00 ,  H04J3/06 ,  H04J3/24 ,  H04L1/24 ,  H04L7/00

CPC classification number: H04L1/243

Abstract: A communication-line-quality measuring system includes transmission and terminal equipment. Transmission equipment has a first frame assembling part transmitting a down-link multiplexed frame signal to a down-link line having a first frequency, and a first frame disassembling part disassembling an up-link multiplexed frame signal transmitted through an up-link line having a second frequency. Terminal equipment has a second frame disassembling part disassembling the down-link multiplexed frame signal, and a second frame assembling part transmitting the up-link multiplexed frame signal obtained by frame-multiplexing an output signal of the subscriber unit with a control signal, to the up-link line. A pattern generation part in the first frame assembling part provides a test signal to an available channel of signal frames in the down-link multiplexed frame signal. A loop-back part between the second frame disassembling part and the frame assembling part loops back the test signal derived from the down-link multiplexed frame signal in the second frame disassembling part to the second frame assembling part. The second frame assembling part provides the test signal in the up-link multiplexed frame signal to transmit to the transmission equipment. A comparing part in the transmission equipment compares the test signal in the up-link multiplexed frame signal, which is looped back by a control of the loop-back part, with a reference signal the same as the test signal generated in the pattern generation part.

Abstract translation: 通信线质量测量系统包括传输和终端设备。 传输设备具有将下行链路多路复用帧信号发送到具有第一频率的下行链路线的第一帧组装部分，以及分解通过上行链路线路发送的上行链路多路复用帧信号的第一帧拆卸部分， 第二频率。 终端设备具有拆卸下行链路多路复用帧信号的第二帧拆卸部分，以及将通过将用户单元的输出信号进行帧多路复用而获得的上行链路复用帧信号的控制信号发送到第二帧组装部分 上行线。 第一帧组合部分中的模式生成部分向下行链路复用帧信号中的信号帧的可用信道提供测试信号。 第二帧分解部与帧组装部之间的环回部将从第二帧分解部的下行链路复用帧信号导出的测试信号回送到第二帧组装部。 第二帧组装部分在上行链路多路复用帧信号中提供测试信号，以传输到传输设备。 传输设备中的比较部分将通过环回部分的控制环回的上行链路复用帧信号中的测试信号与在模式生成部分中生成的测试信号相同的参考信号进行比较 。

公开(公告)号：US5956370A

公开(公告)日：1999-09-21

申请号：US586173

申请日：1996-01-17

Applicant: Francois Ducaroir ,  Rong Pan ,  Krishnan Ramamurthy

Inventor： Francois Ducaroir ,  Rong Pan ,  Krishnan Ramamurthy

IPC: H04L1/24 ,  H04B1/44

CPC classification number: H04L1/243 ,  H04Q2213/13036 ,  H04Q2213/1316 ,  H04Q2213/13162 ,  H04Q2213/13174 ,  H04Q2213/13213 ,  H04Q2213/1332 ,  H04Q2213/13322

Abstract: A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract translation: 公开了一种用于在集成电路上的集成I / O接口核心器件的部分内提供本地故障检测的回绕测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 在将重新格式化传输之前，输入测试数据的回绕到接收机的数据对准阶段允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，在序列化之前将对准模式编码并行数据的回绕到接收机的数据对准阶段允许在I / O收发器的这一部分中识别故障。 本发明的回绕测试系统和方法允许在I / O核心的边界内的故障隔离，而与外部逻辑或测试器无关。

公开(公告)号：US5787114A

公开(公告)日：1998-07-28

申请号：US586174

申请日：1996-01-17

Applicant: Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

Inventor： Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

IPC: G06F11/267 ,  H04L1/24 ,  H04B1/44

CPC classification number: G06F11/2221 ,  H04L1/241 ,  H04L1/243

Abstract: A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract translation: 公开了一种用于在集成电路上的集成I / O接口设备的核心或宏小区内提供本地故障检测的环回测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 输出测试数据从发射机直接输出到接收机输入的回路允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，从I / O发射器的输出级到接收器的输入级的串行化对准模式编码并行数据的回送允许识别在集成I / O收发器宏单元内发生的故障 。 本发明的环回测试系统和方法允许在I / O核心的边界内进行故障隔离，而与外部逻辑或测试器无关。

公开(公告)号：US5737317A

公开(公告)日：1998-04-07

申请号：US454845

申请日：1995-05-31

Applicant: Akira Takayama

Inventor： Akira Takayama

IPC: H04L1/24 ,  H04L7/00 ,  H04Q11/04 ,  H04J1/16 ,  H04J3/14

CPC classification number: H04L1/243 ,  H04L7/0083 ,  H04Q11/045 ,  H04Q2213/1316 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/13214 ,  H04Q2213/13305 ,  H04Q2213/1332

Abstract: A communication system testing method for testing a communication unit including a communication line and components of a communication unit such as a terminal unit. In addition, a control apparatus includes pause control means and control means, both of which are incorporated in an integrated communication control circuit. When the integrated communication control circuit is in the pause state, the pause control means outputs a pause permission indicating signal and detecting signal. The control means discontinues the supply of the main-clock signal by outputting the detecting signal, thereby limiting energy consumption.

Abstract translation: 一种用于测试通信单元的通信系统测试方法，所述通信单元包括通信线路和诸如终端单元的通信单元的部件。 此外，控制装置包括暂停控制装置和控制装置，它们都被并入集成通信控制电路中。 当集成通信控制电路处于暂停状态时，暂停控制装置输出暂停允许指示信号和检测信号。 控制装置通过输出检测信号来中断主时钟信号的供给，从而限制能量消耗。

公开(公告)号：US5477531A

公开(公告)日：1995-12-19

申请号：US162114

申请日：1993-12-13

Applicant: Neil H. McKee ,  Peter Phaal

Inventor： Neil H. McKee ,  Peter Phaal

IPC: H04L1/24 ,  H04L12/26 ,  H04J3/26 ,  H04L1/14

CPC classification number: H04L43/50 ,  H04L1/243 ,  H04L12/2697 ,  H04L43/10

Abstract: In packet-based networks (10), it is often desired to test communications between two specific stations (11, 12). This can generally be effected from a first one of the stations (11) by requesting the other station (12) to `loop-back` a test packet sent from the first station. The first station (11), on receiving back the test packet, can thereby ascertain that not only is communication with the other station (12) possible, but it can also measure the round trip time. However, more complex characteristics of the transmission path between the stations (11, 12) are not ascertainable in this manner. The transmission of a predetermined sequence of packets permits such characteristics to be determined by observing the effect of the network (10) on the sequence considered as a whole. Thus by varying packet size in a sequence, characteristics such as bandwidth, propagation delay, queuing delay and the network's internal packet size can be derived. The use of bursts of packets enables buffer size and re-sequencing characteristics to be determined.

Abstract translation: PCT No.PCT / GB92 / 00967 Sec。 371日期：1993年12月13日 102（e）日期1993年12月13日PCT提交1992年5月28日PCT公布。 第WO92 / 22967号公报 日期为1992年12月23日。在基于分组的网络（10）中，通常希望测试两个特定站点（11,12）之间的通信。 这通常可以通过请求另一站（12）“回送”从第一站发送的测试分组从站（11）中的第一站来实现。 第一站（11）在接收到测试分组时可以确定不仅可以与另一站（12）进行通信，而且还可以测量往返时间。 然而，不能以这种方式确定站（11,12）之间的传输路径的更复杂的特征。 通过观察网络（10）对被认为是整体的序列的影响，可以确定预定的分组序列的传输。 因此，通过在序列中改变分组大小，可以导出诸如带宽，传播延迟，排队延迟和网络内部分组大小之类的特征。 使用分组突发可以确定缓冲区大小和重新排序特性。

公开(公告)号：US5398234A

公开(公告)日：1995-03-14

申请号：US130331

申请日：1993-10-01

Applicant: Anne O'Connell ,  John Hickey ,  John Byrne

Inventor： Anne O'Connell ,  John Hickey ,  John Byrne

IPC: H04J3/12 ,  H04J3/14 ,  H04L1/24 ,  H04M3/24

CPC classification number: H04M3/244 ,  H04J3/125 ,  H04J3/14 ,  H04L1/243

Abstract: Loop-back detection and signalling is achieved on any DS-0 channel that conforms to 56 kbps operation such as DDS in a DS-1 digital data transmission system. A standard DS-1 chip set (line interface unit, framer, and link layer controller) is used, coupled to 24 transmit and receive buffer means in the customer main memory. The framer detects control bits by using Channel Associate Signalling, (designed for digitising voice in-band signalling and not normally used for data transmission), in the incoming signal and interrupts the customer CPU, which determines from the framer which channel caused the interrupt, changes the mode of the relevant channel, checks that channel's receive buffer means for loop-back codes, and, if enough successive loop-back codes are found, copies the receive buffer means into the transmit buffer means (with code mapping) for as long as the loop-back condition exists.

Abstract translation: 在DS-1数字数据传输系统中，符合56 kbps操作（如DDS）的任何DS-0通道均实现环回检测和信令。 使用标准DS-1芯片组（线路接口单元，成帧器和链路层控制器），耦合到客户主存储器中的24个发送和接收缓冲器装置。 成帧器通过使用信道关联信令（设计用于数字化语音带内信令而不是通常用于数据传输）来检测控制位，并中断客户CPU，从客户CPU确定哪个信道导致中断， 改变相关通道的模式，检查通道的接收缓冲区是否为环回代码，并且如果找到足够的连续循环代码，则将接收缓冲器装置复制到发送缓冲器装置（具有代码映射）一段长时间 因为环回条件存在。

公开(公告)号：US5391387A

公开(公告)日：1995-02-21

申请号：US941434

申请日：1992-10-23

Applicant: Michael D. Peters

Inventor： Michael D. Peters

IPC: A23G1/21 ,  A23G3/02 ,  A23G3/20 ,  A23G4/04 ,  H04L1/24 ,  A23G3/00 ,  A23P1/00

CPC classification number: A23G4/04 ,  A23G1/21 ,  A23G3/0263 ,  A23G3/2023 ,  H04L1/243

Abstract: Partially formed products (2) are placed in molds (8) and a fluid such as air or an edible filler is injected into the partially formed products (2), e.g. by needles 17[see FIG. 6], so as to cause expansion and thereby produce final products (2) having the shape of the molds (8). Each mold (8) may comprise an upper mold part (14) and a lower mold part (11). The lower mold parts (11) may be mounted on a chain conveyor (9, 9b, 9c) [see FIG. 1] or a rotating cylinder (28) [see FIG. 12] so that the partially formed products (2) are moved towards and the final products (2) are moved away from a reciprocating assembly (12, 13) which carries the upper mold parts (14). Preferably, the final products (2) are retained in the upper mold parts (14) and then ejected by a blast of air. The invention enables complicated shapes to be formed at high production rates while using an economical amount of chocolate or the like.

Abstract translation: PCT No.PCT / GB92 / 00697 Sec。 371日期：1992年10月23日 102（e）日期1992年10月23日PCT提交1992年4月15日PCT公布。 WO93 / 20705 PCT公开号 日期为1993年10月28日。将部分成型的产品（2）放置在模具（8）中，将诸如空气或可食用填料的流体注入到部分成型的产品（2）中。 通过针17 6]，从而引起膨胀，从而产生具有模具（8）形状的最终产品（2）。 每个模具（8）可以包括上模具部件（14）和下模具部件（11）。 下模具部件（11）可以安装在链式输送机（9,9b，9c）上（参见图1）。 1]或旋转圆筒（28）[参见图1]。 12]，使得部分成型的产品（2）向着移动并且最终产品（2）移动远离承载上模具部件（14）的往复运动组件（12,13）。 优选地，最终产品（2）保留在上模具部件（14）中，然后通过空气鼓风喷射。 本发明能够在使用经济量的巧克力等的同时以高生产率形成复杂的形状。

公开(公告)号：US5347522A

公开(公告)日：1994-09-13

申请号：US730262

申请日：1991-07-12

Applicant: Hisakazu Ohmori

Inventor： Hisakazu Ohmori

IPC: G06F11/08 ,  G06F11/267 ,  H04L1/24

CPC classification number: G06F11/221 ,  G06F11/08 ,  H04L1/241 ,  H04L1/243

Abstract: A method for detecting a PN (Pseudo Noise) pattern for a remote loopback test in a communication system includes the following first through fifth steps. The first step receives a first n-bit pattern (n is an arbitrary number) which is a part of the PN pattern. The second step leftwardly shifts n bits of the first n-bit pattern by a first number of bits, so that a second n-bit pattern is generated. The third step executes an exclusive-OR operation on the n bits of the first n-bit pattern and n bits of the second n-bit pattern, so that a third n-bit pattern is generated. The fourth step rightwardly shifts n bits of the third n-bit pattern by a second number of bits, so that a fourth n-bit pattern is generated. The fifth step executes an exclusive-OR operation on the n bits of the third n-bit patterns and n bits of the fourth n-bit patterns, so that a fifth n-bit pattern is generated. The fifth n-bit pattern is a sixth n-bit pattern which is received after the first n-bit pattern. The first through fifth are repeatedly carried out each time n bits of the first n-bit pattern are received at the first step until a pattern detection signal is generated to activate the loopback test procedure when the fifth n-bit pattern and the sixth n-bit pattern become identical for a number of times.

Abstract translation: 一种用于在通信系统中检测用于远程环回测试的PN（伪噪声）模式的方法包括以下第一至第五步骤。 第一步骤接收作为PN模式的一部分的第一n位模式（n是任意数目）。 第二步向左移动第一n位模式的n位第一位数，从而产生第二n位模式。 第三步骤对第一n位模式的n位和第二n位模式的n位执行异或运算，从而产生第三n位模式。 第四步骤将第三n位模式的n位向右移位第二位数，从而产生第四个n位模式。 第五步骤对第三n位模式的n位和第四n位模式的n位执行异或运算，从而产生第五个n位模式。 第五n位模式是在第一n位模式之后接收的第六个n位模式。 每当在第一步骤中接收到第一n位模式的n位时，重复执行第一至第五，直到产生模式检测信号，以在第五个n位模式和第六个n位模式时产生环回测试程序， 位模式变得相同多次。