摘要:
Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive. An illustrative embodiment uses the invention in a transceiver for high-speed full-duplex (bi-directional simultaneous) signaling over a single channel interconnect. An adaptation algorithm is used at system initialization to train the tap coefficients according to the particular channel characteristics. The invention enables reliable extraction of receive-signals from the inherent ringing induced by the channel interconnect and at higher data rates than previously possible.
摘要:
A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.
摘要:
Aspects of the subject disclosure may include, receiving a plurality of communication signals, and generating, according to the plurality of communication signals, a plurality of electromagnetic waves bound at least in part to a dielectric layer of a conductor. The plurality of electromagnetic waves propagates along the dielectric layer of the conductor without an electrical return path, where each electromagnetic wave of the plurality of electromagnetic waves includes a different portions of the plurality of communication signals, and where the plurality of electromagnetic waves utilizes a signal multiplexing configuration that at least reduces an interference between the plurality of electromagnetic waves. Other embodiments are disclosed.
摘要:
In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
摘要:
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
摘要:
A semiconductor integrated circuit including a waveform shaping circuit is provided. The waveform shaping circuit receives a signal. The waveform shaping circuit operates with a first inductance value in a first period. During the first period, a rising edge or a falling edge of a waveform of the signal is enhanced. The waveform shaping circuit operates with a second inductance value in a second period. During the second period, the rising or falling edges of the waveform is not enhanced. The first inductance value is larger than the second inductance value.
摘要:
A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.
摘要:
A power line communication device including a current path provided between a first terminal and a second terminal. A coupling circuit includes a first circuit of a first inductor connected in parallel with a first capacitor and a first resistor, wherein the coupling circuit is connected between the first and second terminals. A sensor is configured to sense a communication parameter of the coupling circuit. The communication parameter may be a resonance of the first circuit, the quality (Q) factor of the resonance, the bandwidth (BW) of the coupling circuit, the resistance of the first resistor, or the impedance of the first circuit. A transceiver is adapted to couple to the first and second terminal to transmit a signal onto the current path or receive a signal from the current path responsive to the parameter of the coupling circuit and a level of current in the current path sensed by the sensor.
摘要:
A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.
摘要:
A transmission device of the disclosure includes: a transmission symbol generator unit that generates, on the basis of a predetermined number of transition signals each of which indicates a transition in a sequence of transmission symbols, transmission symbol signals that are equal in number to the predetermined number, a serializer unit that serializes the predetermined number of the transmission symbol signals, to generate a serial signal; and a driver unit that operates on the basis of the serial signal.