Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals
    61.
    发明授权
    Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals 有权
    信号流图的低电平实现用于高速数字信号的实时信号处理

    公开(公告)号:US06469988B1

    公开(公告)日:2002-10-22

    申请号:US09349832

    申请日:1999-07-08

    IPC分类号: H04B320

    CPC分类号: H04L5/14 H04L25/0264

    摘要: Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive. An illustrative embodiment uses the invention in a transceiver for high-speed full-duplex (bi-directional simultaneous) signaling over a single channel interconnect. An adaptation algorithm is used at system initialization to train the tap coefficients according to the particular channel characteristics. The invention enables reliable extraction of receive-signals from the inherent ringing induced by the channel interconnect and at higher data rates than previously possible.

    摘要翻译: 信号处理技术通过使用混合模拟和数字电路技术执行炮制FIR滤波器算法的信号流程图,以最先进的电路速度(目前为1.6Gbit / s)的速率应用于数据速率。 多个数模转换器(DAC)产生作为FIR滤波器模型的抽头系数的模拟的模拟电流。 DAC用作各自差分对级的尾电流源的可编程电流源。 作为FIR延迟线抽头信号的模拟的差分延迟信号被连接到差分对级的各个的输入端。 差分对级的输入装置的漏极与公共互补负载电路并联连接。 延迟信号用于将抽头系数电流转向一个或另一个公共负载电路。 与公共负载电路的并联连接用于将每个共同连接的输入设备的电流(如果有的话)相加。 该电流求和是FIR累加器的模拟。 由于抽头系数电流易于编程,滤波器可能是自适应的。 说明性实施例将本发明用于通过单信道互连进行高速全双工(双向同时)信令的收发器。 在系统初始化时使用一种适应算法来根据特定的信道特性训练抽头系数。 本发明能够从由信道互连引起的固有振铃以及比以前更高的数据速率可靠地提取接收信号。

    Transmission-line-voltage control circuit and electronic device
including the control circuit
    62.
    发明授权
    Transmission-line-voltage control circuit and electronic device including the control circuit 失效
    传输线路电压控制电路和包括控制电路的电子设备

    公开(公告)号:US5629645A

    公开(公告)日:1997-05-13

    申请号:US403945

    申请日:1995-03-14

    CPC分类号: H04L25/0264 H04L25/03834

    摘要: A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

    摘要翻译: 公开了一种用于控制传输线的电平的传输线电压控制电路。 指示逻辑高的第一电平的信号和指示逻辑低的第二电平的信号被提供给传输线。 传输线电压控制电路包括连接到传输线的电路。 在将第一电平的信号提供给传输线之后,该电路将传输线的电平降低到指示逻辑高并且小于第一电平的第三电平。 并且在第二电平的信号被提供给传输线之后,电路也增加了传输线的电平到指示逻辑低并且高于第二电平的第四电平。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL PROCESSING DEVICE

    公开(公告)号:US20230308319A1

    公开(公告)日:2023-09-28

    申请号:US17898914

    申请日:2022-08-30

    发明人: Mitsuyuki Ashida

    摘要: A semiconductor integrated circuit including a waveform shaping circuit is provided. The waveform shaping circuit receives a signal. The waveform shaping circuit operates with a first inductance value in a first period. During the first period, a rising edge or a falling edge of a waveform of the signal is enhanced. The waveform shaping circuit operates with a second inductance value in a second period. During the second period, the rising or falling edges of the waveform is not enhanced. The first inductance value is larger than the second inductance value.

    Variable impedance circuit
    68.
    发明授权

    公开(公告)号:US11728845B2

    公开(公告)日:2023-08-15

    申请号:US17230087

    申请日:2021-04-14

    发明人: Ofir Bieber

    摘要: A power line communication device including a current path provided between a first terminal and a second terminal. A coupling circuit includes a first circuit of a first inductor connected in parallel with a first capacitor and a first resistor, wherein the coupling circuit is connected between the first and second terminals. A sensor is configured to sense a communication parameter of the coupling circuit. The communication parameter may be a resonance of the first circuit, the quality (Q) factor of the resonance, the bandwidth (BW) of the coupling circuit, the resistance of the first resistor, or the impedance of the first circuit. A transceiver is adapted to couple to the first and second terminal to transmit a signal onto the current path or receive a signal from the current path responsive to the parameter of the coupling circuit and a level of current in the current path sensed by the sensor.