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99 条记录 (耗时 0.016 秒)

    Range based detection of memory access
    63.
    发明申请
    Range based detection of memory access 有权
    基于范围的内存访问检测

    公开(公告)号：US20040073845A1

    公开(公告)日：2004-04-15

    申请号：US09798596

    申请日：2001-03-02

    发明人： Gary L. Swoboda

    IPC分类号： G06F011/26

    CPC分类号： G01R31/31705 ,  G06F9/455 ,  G06F11/261 ,  G06F11/3466 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/364 ,  G06F11/3648 ,  G06F11/3656 ,  Y02D10/34 ,  Y02T10/82 ,  Y10S370/914

    摘要： Memory accesses in a data processing device (14) can be monitored by selecting, from among a plurality of available memory relationships (37, 82), a memory relationship relative to an address of a reference memory location (B2). When a memory access address bears the selected memory relationship relative to the address, an event (24) can be declared.

    摘要翻译： 可以通过从多个可用存储器关系（37,82）中选择与参考存储器位置（B2）的地址相关的存储器关系来监视数据处理设备（14）中的存储器访问。 当存储器访问地址相对于地址具有选择的存储器关系时，可以声明事件（24）。

    Low latency, low power deserializer
    64.
    发明授权
    Low latency, low power deserializer 有权
    低延迟，低功耗解串器

    公开(公告)号：US06535527B1

    公开(公告)日：2003-03-18

    申请号：US09302193

    申请日：1999-04-29

    申请人： Michael L. Duffy

    发明人： Michael L. Duffy

    IPC分类号： H04J306

    CPC分类号： H03M9/00 ,  H03L7/06 ,  H04J3/0685 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/04 ,  Y10S370/914

    摘要： An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

    摘要翻译： 一种包括第一电路，解串行器电路和成帧器电路的装置。 第一电路可以被配置为响应于具有第一数据速率的输入信号呈现具有第二数据速率的时钟信号和数据信号。 解串行器电路可以包括（a）并行寄存器组，其被配置为响应于（i）时钟信号，（ii）数据信号和（iii）一个或多个选择信号而产生输出信号，以及（b）状态机 被配置为响应于一个或多个控制信号而生成所述一个或多个选择信号。 成帧器电路可以被配置为响应于（i）一个或多个输入控制信号和（ii）输出信号而产生一个或多个控制信号。

    System and method for adaptive multi-rate (AMR) vocoder rate adaption
    65.
    发明授权
    System and method for adaptive multi-rate (AMR) vocoder rate adaption 失效
    自适应多速率（AMR）声码器速率适应的系统和方法

    公开(公告)号：US06529730B1

    公开(公告)日：2003-03-04

    申请号：US09080013

    申请日：1998-05-15

    申请人： Jaleh Komaili ,  Yongbing Wan

    发明人： Jaleh Komaili ,  Yongbing Wan

    IPC分类号： H04Q720

    CPC分类号： H04L1/0011 ,  G10L19/24 ,  H04L1/0014 ,  H04L1/0025 ,  H04L1/0026 ,  H04L1/0059 ,  H04W28/22 ,  H04W88/181 ,  Y10S370/914

    摘要： The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission. The appropriate levels of channel coding necessary for reliable transmission are determined by various channel metrics, such as frame erase rate and bit error rate. The determination of the appropriate vocoder rate and level of channel coding for both the uplink and downlink may be determined centrally at the base station, with the vocoder rate and level of channel coding for the uplink being relayed to the mobile station. Alternatively, the appropriate vocoder rate and level of channel coding for the downlink may be determined by the mobile station, and the appropriate vocoder rate and level of channel coding for the uplink may be determined by the base station.

    摘要翻译： 本发明包括具有基站和至少一个移动站的时分多址（TDMA）通信系统，每个移动站发送和接收携带数字编码语音的模拟射频信号。 使用声码器编码语音，该声码器以可变的编码速率对语音信号进行采样。 在射频信道遇到高信道干扰的期间，选择具有较低编码率的编码语音信道。 这种低速率编码语音与确保可靠传输所必需的高度信道编码相结合。 当射频信道正在经历低信道干扰水平时，需要较少的信道编码，并且使用具有较高编码率的声码器。 高速率编码语音与确保可靠传输所必需的较低信道编码相结合。 可靠传输所需的适当级别的信道编码由各种信道量度来确定，例如帧擦除率和误码率。 可以在基站中央确定适当的声码器速率和上行链路和下行链路的信道编码级别，其中声码器速率和上行链路的信道编码级别被中继到移动台。 或者，可以由移动台确定下行链路的适当的声码器速率和信道编码级别，并且可以由基站确定上行链路的适当的声码器速率和信道编码级别。

    Circuit arrangement for bit rate adaptation
    66.
    发明授权
    Circuit arrangement for bit rate adaptation 失效
    比特率调整的电路布置

    公开(公告)号：US5327430A

    公开(公告)日：1994-07-05

    申请号：US993259

    申请日：1992-12-18

    申请人： Ralph Urbansky

    发明人： Ralph Urbansky

    IPC分类号： H04J3/00 ,  H04J3/07 ,  H04L7/00 ,  H04J3/06

    CPC分类号： H04J3/076 ,  Y10S370/914

    摘要： A circuit arrangement for adapting the bit rates of two signals to each other comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7, 8). In order to largely avoid jitter in the signal that has been read, the read address counter (8) and the phase comparator (16) are incorporated in a control circuit that controls the clock for the read address counter (8). In this control circuit the output signal of the phase comparator (16) is the control error. The controlled system (17) of the control circuit consists of a controllable oscillator circuit with whose output signal and read address counter (8) is clocked. In order to avoid stationary phase shifts with a constant frequency shift, a controller (18) having a PI behavior (PI=proportionality and integration) is used.

    摘要翻译： 用于使两个信号的比特率彼此适配的电路装置包括弹性存储器（6）。 通过写地址计数器（7）将第一帧结构信号的有用数据写入该存储器（6），并通过读地址计数器（8）再次读出。 相位比较器（16）用于比较这些计数器（7,8）的计数。 为了在很大程度上避免已经读出的信号中的抖动，读地址计数器（8）和相位比较器（16）被并入控制读地址计数器（8）的时钟的控制电路中。 在该控制电路中，相位比较器（16）的输出信号是控制误差。 控制电路的控制系统（17）由可控振荡器电路组成，其输出信号和读地址计数器（8）被计时。 为了避免具有恒定频移的固定相移，使用具有PI行为（PI =比例和积分）的控制器（18）。

    Key telephone system
    67.
    发明授权
    Key telephone system 失效
    关键电话系统

    公开(公告)号：US5193089A

    公开(公告)日：1993-03-09

    申请号：US443151

    申请日：1989-11-30

    申请人： Shinji Tsuchida

    发明人： Shinji Tsuchida

    IPC分类号： H04Q3/58 ,  H04J3/02 ,  H04M11/00

    CPC分类号： H04J3/02 ,  Y10S370/914

    摘要： A key telephone system is provided with a main equipment including at least two extensions and at least one line wire which accommodates a digital line. The key telephone system is arranged to enable reciprocal data communications by effecting speed matching in data communications between a data terminal connected to the extension and the digital line accommodated in the line wire.

    摘要翻译： 钥匙电话系统设置有包括至少两个延伸部的主设备和容纳数字线路的至少一条线路线。 密钥电话系统被布置为通过在连接到分机的数据终端与容纳在线路线中的数字线路之间的数据通信中实现速度匹配来实现互换数据通信。

    Full duplex modem system for differing data bit rates
    69.
    发明授权
    Full duplex modem system for differing data bit rates 失效
    全双工调制解调器系统，用于不同的数据比特率

    公开(公告)号：US4882726A

    公开(公告)日：1989-11-21

    申请号：US123941

    申请日：1987-11-23

    申请人： Gordon R. Lang ,  Fred M. Longstaff

    发明人： Gordon R. Lang ,  Fred M. Longstaff

    IPC分类号： H04L25/05 ,  H04L25/49

    CPC分类号： H04L25/4908 ,  H04L25/05 ,  Y10S370/914

    摘要： A pair of full duplex modems are connected and each is designed to transmit to the other at the same predetermined band rates. One modem is connected to receive data bits for transmission over the channel at a predetermined first (and fast) rate and to transmit its received data bits at a integral number of first transmission bits per band. The other modem is connected to receive data bits for transmission over the channel at a rate slower than the band rate and is designed to sequentially encode blocks of said slower rate data bits into a larger number of second transmission bits for transmission over said channel at an integral number of second transmission bits per band. Means forming part of said one modem for converting said second transmission bits into the slower rate data bits.

    摘要翻译： 一对全双工调制解调器被连接，并且每个都被设计成以相同的预定频带速率传输到另一个。 连接一个调制解调器以接收用于以预定的第一（和快速）速率在信道上传输的数据位，并以每个频带的整数个第一传输位发送其接收的数据位。 另一个调制解调器被连接以接收数据比特以便以比该频带速率慢的速率在该信道上进行传输，并且被设计为将所述较慢速率数据比特的比特顺序地编码为更大数量的第二传输比特，以便在所述信道上传输 每个频带的第二个传输比特数的整数。 形成所述一个调制解调器的一部分的装置，用于将所述第二传输比特转换成较慢速率的数据比特。

    Conference circuit
    70.
    发明授权
    Conference circuit 失效
    会议电路

    公开(公告)号：US4479212A

    公开(公告)日：1984-10-23

    申请号：US357773

    申请日：1982-03-12

    申请人： Andres Albanese

    发明人： Andres Albanese

    IPC分类号： H04J3/04 ,  H04M3/56 ,  H04Q11/04 ,  H04J3/02

    CPC分类号： H04M3/561 ,  Y10S370/914

    摘要： In a digital, time division multiplex communication system, a first-in, first-out buffer (10) at each subscriber station is employed to establish a conference call. The digital words of the conferees being listened to are entered into the buffer as they are received. They are then read out at a different bit rate such that they all occupy an equal fraction of the word period. The words are decoded in a standard D/A converter (11) and combined in a filter (12).

    摘要翻译： 在数字时分复用通信系统中，采用每个用户站的先入先出缓存（10）来建立会议呼叫。 正在收听的与会者的数字字在收到时被输入缓冲区。 然后，它们以不同的比特率读出，使得它们都占据单词周期的相等分数。 这些字在标准D / A转换器（11）中解码，并组合在一个滤波器（12）中。