公开(公告)号：US20190121740A1

公开(公告)日：2019-04-25

申请号：US15790297

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Sidheshkumar Ramanlal Patel ,  Sneha Kishor Wagh

IPC: G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F15/78 ,  G06F5/06 ,  G06F12/0873 ,  G06F12/1027 ,  G06F12/1009

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

公开(公告)号：US20190087369A1

公开(公告)日：2019-03-21

申请号：US15709550

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Syed Naseef ,  Ghanashyam Prabhu

IPC: G06F13/28 ,  G06F13/16 ,  G06F5/06 ,  G06F13/42 ,  G06F13/24

Abstract: Full-duplex memory access systems and methods for improved quality of service (QoS) are disclosed. In one aspect, a primary bus owner will evaluate an output from a secondary bus owner when the primary bus owner takes control of the bus to determine if the secondary bus owner has data to send to the primary bus owner and/or is in the midst of a bulk data transfer. If the evaluation determines that there is still data to be transferred, the primary bus owner may refrain from draining an internal register unless a full word is present in the register. By reducing memory access for a partial word in the register, QoS may be improved.

公开(公告)号：US10198387B2

公开(公告)日：2019-02-05

申请号：US15163310

申请日：2016-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Hyung Chung ,  Cheol-Ho Lee ,  Dong-Ho Yu ,  Dae-Woong Kim

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F5/06 ,  G06F9/4401 ,  G06F13/42

Abstract: An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength of signals communicated according to changed modes are provided. The method includes detecting a connection with an external device corresponding to booting of the electronic device, determining a mode of the electronic device according to the detected connection with the external device, varying a characteristic setting of an input output (IO) buffer to a certain strength corresponding to the determined mode, and communicating a signal at a strength corresponding to the varied setting.

公开(公告)号：US20190033909A1

公开(公告)日：2019-01-31

申请号：US16149987

申请日：2018-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-JIN CHO ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

IPC: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

公开(公告)号：US10191529B2

公开(公告)日：2019-01-29

申请号：US15355808

申请日：2016-11-18

Applicant: Accenture Global Services Limited

Inventor： Qin Zhou ,  Zhihui Yang ,  Xiaopei Cheng ,  Yan Gao ,  Guo Ma

IPC: G06F1/32 ,  G06F5/14 ,  G06F17/30 ,  G06F1/26 ,  G06F11/30 ,  G06F11/34 ,  H04L12/861 ,  G06F5/06 ,  H04L12/879 ,  G06F3/06 ,  G06F12/02

Abstract: A real-time data management system for accessing data in a power grid that controls a transmission delay of real-time data delivered via a real-time bus, and delivers real-time data in a power grid. A unified data model covering various organizations and various data resource may be included. Multi-bus collaboration and bus performance optimization approaches may be used to improve efficiency and performance of the buses. An event integration and complex event process component may be included to provide status of the power grid. A high volume of real-time data and events may be managed to provide data transmission with a low latency, provide flexible extension of the number of data clusters and the number of databases to ensure high volume data storage, and achieve a high speed and transparent data access. Additionally, rapid design and development of analytical applications, and the near real-time enterprise decision-making may be enabled.

公开(公告)号：US10157649B1

公开(公告)日：2018-12-18

申请号：US15046005

申请日：2016-02-17

Applicant: MARVELL ISRAEL (M.I.S.L) LTD.

Inventor： Ohad Zalcman

IPC: G11C7/10 ,  G06F5/06 ,  G06F1/32

Abstract: Aspects of the disclosure provide a first-in-first-out (FIFO) circuit having a memory block and a logic circuit. The memory block includes an array of memory cells configured to be able to store N data entries in a FIFO order (N is a positive integer). The logic circuit is configured to compare input data with previously input data to detect a number of consecutive identical entries of input data, and suppress an operation of selected memory cells when the number is larger than N.

公开(公告)号：US20180341459A1

公开(公告)日：2018-11-29

申请号：US15607437

申请日：2017-05-27

Applicant: International Business Machines Corporation

Inventor： Gregg L. Liguori ,  Franklin E. McCune ,  David C. Reed ,  Michael R. Scott

IPC: G06F5/06 ,  H04L12/875

Abstract: A method for allocating a resource to multiple requesters is disclosed. In one embodiment, such a method includes maintaining, for a resource, a regular queue and an express queue. The method receives requests to control the resource and determines, for each request, an anticipated amount of time that the request needs to control the resource. In the event the anticipated amount of time for a request is greater than a selected threshold, the method allocates the request to the regular queue. In the event the anticipated amount of time for a request is less than the selected threshold, the method allocates the request to the express queue. The method provides priority to requests allocated to the express queue over requests allocated to the regular queue. A corresponding system and computer program product are also disclosed.

公开(公告)号：US10133298B2

公开(公告)日：2018-11-20

申请号：US14995834

申请日：2016-01-14

Applicant: Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

Inventor： Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

IPC: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

公开(公告)号：US10101963B2

公开(公告)日：2018-10-16

申请号：US15238240

申请日：2016-08-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Eric Thomas ,  Jennifer Veronica Hack ,  David Maciorowski

IPC: G06F13/36 ,  G06F9/46 ,  G06F5/06 ,  G06F13/16 ,  G06F13/40

Abstract: Some examples comprise a memory device including a memory region accessible by a receiving processing unit and a plurality of sending processing units, the memory region including a set of memory buffers identified by a set of buffer identifiers; a first FIFO buffer for communicating a first buffer identifier from the receiving processing unit to any of the sending processing units, the first buffer identifier corresponding to a memory buffer available for use by the any one sending processing unit in sending data to the receiving processing unit; and a second FIFO buffer for communicating a second buffer identifier to the receiving processing unit from any of the sending processing units, the second buffer identifier corresponding to a memory buffer containing data being sent to the receiving unit.

公开(公告)号：US10056132B1

公开(公告)日：2018-08-21

申请号：US15045207

申请日：2016-02-16

Applicant: Seagate Technology LLC

Inventor： Todd Michael Lammers ,  Robert Matousek

IPC: G06F5/16 ,  G11C11/4096 ,  G11C11/4076 ,  G11B5/02 ,  G06F5/06 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/16 ,  H03M1/0636 ,  H03M1/12 ,  H03M1/1265

Abstract: Amplifiers, preamplifiers, and other circuits may have registers that are assigned to store data corresponding to certain functions. When the data stored in the registers are no longer needed, the registers may be assigned to store data corresponding to other functions, such as signal acquisition. The registers can be logically grouped into a virtual memory bank. The memory bank may store new data to a first register, and move data from the first register to a second register when new data arrives. In some embodiments, these registers and memory control circuit can be implemented within a preamplifier circuit.