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公开(公告)号：US11973511B2
公开(公告)日：2024-04-30
申请号：US17817636
申请日：2022-08-04
发明人： Ting-Hao Wang , Hsin-Han Han
CPC分类号： H03M1/1023 , H03M1/0636 , H03M1/1215 , H03M1/126
摘要： An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.
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公开(公告)号：US20110291872A1
公开(公告)日：2011-12-01
申请号：US13056933
申请日：2008-07-31
申请人： Stephane Pinel , Joy Laskar
发明人： Stephane Pinel , Joy Laskar
IPC分类号： H03M1/12
CPC分类号： H03M1/361 , H03K5/08 , H03K5/2472 , H03M1/0636 , H03M1/1215 , H03M1/20
摘要： An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.
摘要翻译： 可以使用微比较器/采样器，编码器和选择器来实现用于高速操作的模数转换器。 微型比较器包括来自接收器/收发器系统的天线的输入; 晶体管对; 复位晶体管; 级联逆变器; 逆变器电路; 一个缓冲区 和D触发电路。 根据并行放置的微比较器/采样器的数量，可以产生多个位。 例如，15个不同的微比较器/采样器的15位可以插入15到4位编码器中，以生成4位。
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公开(公告)号：US20110210763A1
公开(公告)日：2011-09-01
申请号：US12869234
申请日：2010-08-26
IPC分类号： G11C27/02
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
摘要翻译： 拒绝采样器/转换器中的输入共模电压变化的方法，其避免在信号路径中使用差分放大器，并且不引入附加的失真或噪声。 在一个实施例中，在节点“Vcmi”上跨越共模模拟输入的一对匹配电阻上感测输入共模变化。 一种替代的基于开关电容器的感测方案也是可能的。 使用该测量的Vcmi，然后对采样器/转换器的其余部分进行调整，以取出在Vcmi处观察到的任何变化。
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4.发明授权公开(公告)号：US09673832B2
公开(公告)日：2017-06-06
申请号：US15134866
申请日：2016-04-21
申请人： MediaTek Inc.
发明人： Chihhou Tsai
CPC分类号： H03M1/08 , H03M1/0636 , H03M1/462 , H03M1/468
摘要： A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.
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5.发明申请公开(公告)号：US20160336954A1
公开(公告)日：2016-11-17
申请号：US15134866
申请日：2016-04-21
申请人： MediaTek Inc.
发明人： Chihhou TSAI
CPC分类号： H03M1/08 , H03M1/0636 , H03M1/462 , H03M1/468
摘要： A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.
摘要翻译： 公开了一种具有高精度的逐次逼近寄存器模数转换器（SAR ADC）。 在SAR ADC内，SAR逻辑电路组合在模拟输入的数字表示的搜索方案的多个循环的至少两个连续周期期间收集的比较器的输出信号，并且因此，对 比较器的正输入端和负输入端之间的电压差。 SAR ADC的电容网络至少有三个电容网络切换选择由一步控制提供。 通过一步控制，根据在至少两个连续循环期间获得的比较器的至少两个比较结果，在至少三个电容器网络切换选择之间进行选择。 以这种方式，利用比较器噪声作为附加量化电平来提高整体ADC噪声性能。
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公开(公告)号：US20160248434A1
公开(公告)日：2016-08-25
申请号：US14625755
申请日：2015-02-19
发明人： Assaf Govari
CPC分类号： H03M1/0636 , A61B5/04012 , A61B5/0402 , A61B5/042 , A61B5/7203 , A61B2562/18 , G06K9/0051 , H03M1/34 , H04B15/005
摘要： A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized signal. The method also includes recovering a first amplitude and a first phase of the noise from the digitized signal, and generating an analog correction signal at the specific noise frequency. The analog correction signal has a second amplitude equal to the first amplitude and a second phase opposite to the first phase. The method further includes summing the input analog signal with the analog correction signal to generate an output analog signal.
摘要翻译： 一种方法，包括接收包含特定噪声频率的噪声的输入模拟信号，并对所输入的模拟信号进行数字化以形成数字化信号。 该方法还包括从数字化信号中恢复噪声的第一幅度和第一相位，以及以特定噪声频率产生模拟校正信号。 模拟校正信号具有等于第一幅度的第二幅度和与第一相位相反的第二相位。 该方法还包括将输入模拟信号与模拟校正信号相加以产生输出模拟信号。
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公开(公告)号：US08183889B2
公开(公告)日：2012-05-22
申请号：US12869234
申请日：2010-08-26
IPC分类号： G11C27/02
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
摘要翻译： 拒绝采样器/转换器中的输入共模电压变化的方法，其避免在信号路径中使用差分放大器，并且不引入附加的失真或噪声。 在一个实施例中，在节点“Vcmi”上跨越共模模拟输入的一对匹配电阻上感测输入共模变化。 一种替代的基于开关电容器的感测方案也是可能的。 使用该测量的Vcmi，然后对采样器/转换器的其余部分进行调整，以取出在Vcmi处观察到的任何变化。
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公开(公告)号：US07893857B2
公开(公告)日：2011-02-22
申请号：US12345880
申请日：2008-12-30
申请人： Sung Mook Kim
发明人： Sung Mook Kim
IPC分类号： H03M1/12
CPC分类号： H03K5/2481 , H03M1/0636 , H03M1/42
摘要： Disclosed is a flash analog to digital converter (ADC) capable of reducing area requirements and using successive approximation. The ADC includes a reference voltage generating unit receiving an external voltage and outputting M reference voltages. A reference voltage selecting unit outputs N reference voltages less than the number of the voltages outputted by the reference voltage generating unit according to a supplied control signal. A digital signal output unit compares the N reference voltages outputted by the reference voltage selecting unit with an external analog input signal and outputs the comparison result as an N-bit digital signal.
摘要翻译： 公开了一种能够减少面积要求并使用逐次逼近的闪存模数转换器（ADC）。 ADC包括接收外部电压并输出M个参考电压的参考电压产生单元。 参考电压选择单元根据提供的控制信号输出小于由参考电压产生单元输出的电压数量的N个参考电压。 数字信号输出单元将参考电压选择单元输出的N个参考电压与外部模拟输入信号进行比较，并将比较结果作为N位数字信号输出。
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公开(公告)号：US20070080844A1
公开(公告)日：2007-04-12
申请号：US11543259
申请日：2006-10-05
IPC分类号： H03M1/12
CPC分类号： H03M1/1019 , H03M1/0636 , H03M1/0678 , H03M1/1225 , H03M1/20 , H03M1/50 , H03M1/502 , H03M1/60
摘要： In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.
摘要翻译： 在模拟 - 数字转换器中，生成单元基于模数转换特性曲线执行第一输入信号和第二输入信号的模数转换，分别产生第一数字数据和第二数字数据 对应于第一输入信号和第二输入信号。 输入信号具有第一电平，第一电平是用于模数转换的目标模拟信号的偏移电平和电平之和。 第二输入信号具有第二电平，并且通过从目标模拟信号的电平减去偏移电平来产生第二电平。 在模数转换器中，获取单元获得第一数字数据和第二数字数据之间的差数字数据，以将获得的差分数字数据作为目标模拟信号的数字数据输出。
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公开(公告)号：US20230290398A1
公开(公告)日：2023-09-14
申请号：US17694442
申请日：2022-03-14
CPC分类号： G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1693 , H03M1/0636
摘要： A method for reducing noise in a read signal due attributable to read element asymmetry provides for transmitting a write signal through a write precompensation circuit that shifts rising edges and falling edges of each of pulse in the write signal by a select magnitude and in opposite directions. After the write signal is encoded on a media, a corresponding read signal is read, with a read element, from the media. The method further provides for transmitting the read signal through a magnetoresistive asymmetry compensation (MRAC) block that is tuned to correct second-order non-linearities characterized by a particular set of distortion signatures. The select magnitude of the waveform shift applied by the write precompensation circuit introduces a non-linear signal characteristic that combines with non-linear signal characteristics introduced by the read element to generate one of the particular distortion signatures that is correctable by the MRAC block.
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