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公开(公告)号：US20200186135A1
公开(公告)日：2020-06-11
申请号：US16707881
申请日：2019-12-09
摘要： A method of calibrating a delay generation circuit and the corresponding circuit.
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公开(公告)号：US20200169300A1
公开(公告)日：2020-05-28
申请号：US16654980
申请日：2019-10-16
发明人： BYEONG-TAEK MOON , JUN-HO KIM , YOUNG-JOO LEE
摘要： A near-field communication (NFC) circuit includes a transmitter that generates a transmission signal based on a reference clock signal and transmits the transmission signal through an antenna; a clock recovery circuit that receives a detection signal through the antenna responsive to the transmission signal and recovers a recovered clock signal from the detection signal; a phase detector that detects a phase change of the recovered clock signal; and a controller that determines, based on the phase change of the recovered clock signal, whether an NFC tag external to the NFC circuit is located within a communication range of the NFC circuit.
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公开(公告)号：US20200143853A1
公开(公告)日：2020-05-07
申请号：US16178346
申请日：2018-11-01
申请人： Intel Corporation
发明人： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
摘要： An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US20200112292A1
公开(公告)日：2020-04-09
申请号：US16153324
申请日：2018-10-05
发明人： Chih-Wei LIANG
摘要： An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.
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公开(公告)号：US20200106429A1
公开(公告)日：2020-04-02
申请号：US16143493
申请日：2018-09-27
摘要： Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.
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66.发明授权公开(公告)号：US10598776B2
公开(公告)日：2020-03-24
申请号：US15639049
申请日：2017-06-30
发明人： Ming-Han Weng , Wei-Yung Wang , Chih-Hung Lin , Jyun Yang Shih , Chun-Chia Chen
摘要： An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.
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公开(公告)号：US10587253B1
公开(公告)日：2020-03-10
申请号：US16205093
申请日：2018-11-29
发明人： Yu Huang , Nam Dang , Keith Alan Bowman , Navid Toosizadeh
摘要： A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.
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公开(公告)号：US10587251B2
公开(公告)日：2020-03-10
申请号：US16131227
申请日：2018-09-14
发明人： Ou He , Yan S H He , Wei A W Zhao
摘要： The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.
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公开(公告)号：US20200052708A1
公开(公告)日：2020-02-13
申请号：US16057807
申请日：2018-08-07
申请人： Apple Inc.
发明人： Utku Seckin , Simone Gambini , Benjamin W. Cook
摘要： A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.
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公开(公告)号：US20200044638A1
公开(公告)日：2020-02-06
申请号：US16504534
申请日：2019-07-08
发明人： John Paul LESSO
摘要： This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.
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