公开(公告)号：US09788453B2

公开(公告)日：2017-10-10

申请号：US14950846

申请日：2015-11-24

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chung-Ta Huang ,  Chih-Wei Lee

IPC: H05K7/14

CPC classification number: H05K7/1492

Abstract: A server includes a chassis, a power bridge module having a first power connector, a backplate having a first signal connector, a tray, a motherboard module and a signal bridge board. The motherboard module is fixed to the tray, and includes a second power connector detachably and electrically connected to the first power connector. The signal bridge board includes a second signal connector detachably and electrically connected to the first signal connector. Removal of the tray out of the chassis results in removal and electrical disconnection of the second signal connector from the first signal connector, and removal and electrical disconnection of the second power connector from the first power connector.

公开(公告)号：US09710284B1

公开(公告)日：2017-07-18

申请号：US15013832

申请日：2016-02-02

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Bo-Wen Huang ,  Kei-Way Chang ,  Shih-Ta Chu ,  Jun-Jie Wu ,  Chen-Nan Hsiao

IPC: G06F15/177 ,  G06F9/44 ,  G06F9/445

CPC classification number: G06F9/4403 ,  G06F1/24 ,  G06F8/65 ,  G06F8/654 ,  G06F9/44505

Abstract: A system includes a programmable non-volatile memory, a switch, a control chipset, and a basic input/output (BIOS) module. The switch has a first terminal coupled to the programmable non-volatile memory, and a second terminal coupled to the control chipset. The control chipset is configured to store a SKU parameter set in the programmable non-volatile memory according to a predetermined memory allocation. The BIOS module is coupled to the control chipset, and is configured to load and update the SKU parameter set according to the predetermined memory configuration during a booting operation of the motherboard.

公开(公告)号：US09679611B2

公开(公告)日：2017-06-13

申请号：US14868077

申请日：2015-09-28

Applicant: MiTAC Computing Technology Corporation

Inventor： Yi-Hao Hong ,  Che-Wei Chang ,  Chi-Hsing Wang ,  Hsin-Ta Huang

IPC: G06F3/06 ,  G11B33/10 ,  G08B21/18 ,  G08B5/22 ,  G06F13/38

CPC classification number: G11B33/10 ,  G08B5/22 ,  G08B21/18

Abstract: A method implemented by a status-monitoring device connected between a storage device and a corresponding output unit includes: a) determining presence of a storage device according to a first packet from the storage device; b) when it is determined that the storage device is present, generating a pulse signal according to a second packet from the storage device; c) generating a driving signal indicating a status associated with the storage device according to at least a logic level of the pulse signal; and d) sending the driving signal to the output unit for driving the output unit to output an output signal indicating the status.

公开(公告)号：US20170150635A1

公开(公告)日：2017-05-25

申请号：US14950846

申请日：2015-11-24

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chung-Ta Huang ,  Chih-Wei Lee

IPC: H05K7/14 ,  H05K7/20

CPC classification number: H05K7/1492

Abstract: A server includes a chassis, a power bridge module having a first power connector, a backplate having a first signal connector, a tray, a motherboard module and a signal bridge board. The motherboard module is fixed to the tray, and includes a second power connector detachably and electrically connected to the first power connector. The signal bridge board includes a second signal connector detachably and electrically connected to the first signal connector. Removal of the tray out of the chassis results in removal and electrical disconnection of the second signal connector from the first signal connector, and removal and electrical disconnection of the second power connector from the first power connector.

公开(公告)号：US20170123930A1

公开(公告)日：2017-05-04

申请号：US15293402

申请日：2016-10-14

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Jen-Chih LEE ,  Kwang-Chao CHEN

IPC: G06F11/14 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F11/30

CPC classification number: G06F11/1441 ,  G06F11/3027 ,  G06F11/3051 ,  G06F13/24 ,  G06F13/364 ,  G06F13/4282

Abstract: A method for data communication within an I2C system is provided. The method includes the steps of: a) generating a communication error code indicative of error status when data transmission from a master module to a slave module via an I2C bus fails; b) determining whether to retransmit the data to the slave module according to the communication error code; c) when the determination made in step c) is affirmative, determining whether a number of times of data retransmission(s) associated with the data reaches a predetermined number; d) when the determination made in step c) is affirmative, resetting the master module; and e) recording a communication error event according to the communication error code after step a).

公开(公告)号：US12282560B2

公开(公告)日：2025-04-22

申请号：US18191492

申请日：2023-03-28

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Ming-Chang Tu

IPC: G06F21/57 ,  G06F9/4401

Abstract: A method for blocking an external boot device, a non-transient computer readable storage medium, and a computer are provided. The method includes: executing BIOS program code in a POST process, where the program code includes a BIOS setup menu, which includes a boot device option; hiding device information of an external boot device in the boot device option when determining that the external boot device is classified as a restricted device; displaying a boot device menu when determining that received input information is consistent with a piece of hot key information, where the boot device menu includes the device information of the external boot device; displaying a password input window when determining that the external boot device corresponding to received selection information is classified as the restricted device; and reading the external boot device to execute operating system program code when determining that received password information matches a preset password.

公开(公告)号：US20250103114A1

公开(公告)日：2025-03-27

申请号：US18890378

申请日：2024-09-19

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Yu-Zhe CHIANG

IPC: G06F1/26

Abstract: A method of managing power supply for a server system includes steps of: A) selecting a to-be-processed item from among first power-on items of first power-on sequence data, and determining whether there is at least one batch-processed item among second power-on items of second power-on sequence data according to the to-be-processed item; B) when it is determined that there is at least one batch-processed item, performing a power-on procedure related to the to-be-processed item and transmitting a power-on notification to a system board; C) transmitting a result request to the system board; D) in response to receipt of a power-on result responded by the system board, determining whether at least one power-on state indicates success; and E) when it is determined that the at least one power-on state indicates success, repeating steps A) to D) until all of the first power-on items have been selected.

公开(公告)号：US20240319821A1

公开(公告)日：2024-09-26

申请号：US18585896

申请日：2024-02-23

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Cheng HSUEH

IPC: G06F3/041

CPC classification number: G06F3/0418

Abstract: A touchscreen calibration method and a readable storage media are provided. The method includes: A processor accesses a system administrative events database, which is configured to record a pointer error event; and the processor executes a calibration process when the processor determines the pointer error event does exist. The calibration process includes: disabling a plurality of touchscreens; re-enabling the plurality of touchscreens after a preset time period; loading an apparatus registry file after the plurality of touchscreens are restarted; and establishing connections between the processor and the plurality of touchscreens based on the apparatus registry file.

公开(公告)号：US20240303066A1

公开(公告)日：2024-09-12

申请号：US18453805

申请日：2023-08-22

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chia-Hang CHUNG

IPC: G06F8/65

CPC classification number: G06F8/65

Abstract: A server system and a firmware updating method thereof are provided. The server system includes a first module and a second module. The first module includes a first logic circuit and a first selection circuit. The second module includes a second logic circuit, a second selection circuit, a control circuit, and a storage circuit. The first selection circuit is configured to select the transmission target of the first logic circuit according to a first control signal. The second selection circuit is configured to select the transmission target of the second logic circuit according to a second control signal. The control circuit is configured to update the firmware of the first logic circuit and the firmware of the second logic circuit. The storage circuit is configured to store a support list having default usage codes, and each of the default usage codes indicates a corresponding one of target devices.

公开(公告)号：US20240264824A1

公开(公告)日：2024-08-08

申请号：US18424241

申请日：2024-01-26

Applicant: Mitac Computing Technology Corporation

Inventor： Cheng-Wei SUN

IPC: G06F8/654

CPC classification number: G06F8/654

Abstract: A method of updating a firmware of a computer including a motherboard that has a BMC and a first CPLD, and a backplane that has a second CPLD having a flash memory. The method including steps of: the first CPLD changing a logical value of a signal when the first CPLD determines that a power of the computer is in a desired range; the BMC receiving the signal, and being initiated once the logical value of the signal has been changed; when the BMC is to update a firmware of the second CPLD, the BMC changing a logical value of a register of the first CPLD; and when the first CPLD determines that the logical value of the register has been changed, the first CPLD decoding and verifying a firmware code that is received from the BMC, and updating the firmware code thus decoded and verified to the flash memory.