公开(公告)号：US09153302B2

公开(公告)日：2015-10-06

申请号：US13362847

申请日：2012-01-31

Applicant: Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

Inventor： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/18 ,  G11C11/419 ,  G11C2207/005

Abstract: A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.

Abstract translation: 存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。 每个存储块包括一对位线和耦合到该对位线的多个存储器单元。 每个全局位线耦合到至少一个存储器块。 预充电电路被配置为将全局位线一次一个地预充电到预充电电压。 选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。

公开(公告)号：US08942053B2

公开(公告)日：2015-01-27

申请号：US13535075

申请日：2012-06-27

Applicant: Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

Inventor： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC: G11C7/02 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current mirror circuit is coupled to the first node, and the mirrored end of the first current mirror circuit is coupled to the second node. The second current mirror circuit has a reference end and a mirrored end. The reference end of the second current mirror circuit is coupled to the second node, and the mirrored end of the second current mirror circuit is coupled to the first node.

Abstract translation: 电路包括第一节点，第二节点，第一电流镜电路和第二电流镜电路。 第一电流镜电路具有参考端和镜像端。 第一电流镜电路的参考端耦合到第一节点，并且第一电流镜电路的镜像端耦合到第二节点。 第二电流镜电路具有参考端和镜像端。 第二电流镜电路的参考端耦合到第二节点，并且第二电流镜电路的镜像端耦合到第一节点。

公开(公告)号：US08659090B2

公开(公告)日：2014-02-25

申请号：US13335569

申请日：2011-12-22

Applicant: Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

Inventor： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

Abstract translation: 器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。 第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。 接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。 层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。 第一接触插塞在第一源极/漏极区域上电连接。 第二接触插塞在第二源极/漏极区域之上并对齐。 第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

公开(公告)号：US20130258747A1

公开(公告)日：2013-10-03

申请号：US13437081

申请日：2012-04-02

Applicant: Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

IPC: G11C17/00 ,  G11C11/00 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

公开(公告)号：US20130161707A1

公开(公告)日：2013-06-27

申请号：US13335569

申请日：2011-12-22

Applicant: Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

Inventor： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

Abstract translation: 器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。 第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。 接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。 层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。 第一接触插塞在第一源极/漏极区域上电连接。 第二接触插塞在第二源极/漏极区域之上并对齐。 第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

公开(公告)号：US08437210B2

公开(公告)日：2013-05-07

申请号：US13030722

申请日：2011-02-18

Applicant: Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

Inventor： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

IPC: G11C7/00

CPC classification number: G11C7/08 ,  G11C7/065

Abstract: A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

Abstract translation: 电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。 第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。 第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。 电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。 第二电容大于第一电容。

公开(公告)号：US08355277B2

公开(公告)日：2013-01-15

申请号：US13008992

申请日：2011-01-19

Applicant: Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Hsu-Shun Chen ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C11/413 ,  G11C5/14

CPC classification number: G11C11/413

Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

Abstract translation: SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US20120206953A1

公开(公告)日：2012-08-16

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

IPC: G11C5/06 ,  H01L25/00

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US08223571B2

公开(公告)日：2012-07-17

申请号：US12839575

申请日：2010-07-20

Applicant: Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

Inventor： Chung-Ji Lu ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Derek C. Tao ,  Annie-Li-Keow Lum ,  Hong-Chen Cheng

IPC: G11C7/02

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.

Abstract translation: 电路包括具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

公开(公告)号：US08174911B2

公开(公告)日：2012-05-08

申请号：US12708923

申请日：2010-02-19

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。