Surface plasmon resonance sensor with high sensitivity
    71.
    发明申请
    Surface plasmon resonance sensor with high sensitivity 审中-公开
    表面等离子体共振传感器具有高灵敏度

    公开(公告)号:US20060197952A1

    公开(公告)日:2006-09-07

    申请号:US10660833

    申请日:2003-09-12

    CPC classification number: G01N21/658 G01N21/554

    Abstract: A high-sensitivity SPR (surface plasmon resonance) sensor includes at least a prism having a first surface on which a metallic layer and a metallic nanoparticle layer are sequentially formed. A light source projects an incident light into the prism through a second surface of the prism. The light is reflected by the metallic layer and the metallic nanoparticle layer and leaves the prism through a third surface of the prism. A light detector detects the reflected light. The SPR sensor has an extensive detection range as compared with the conventional ones and is applicable in the detection of gas, chemical substance, and biomolecule. Moreover, the SPR sensor is advantageous in arranging fabrication process consistently, controlling film thickness, improving product quality, and decreasing fabrication cost.

    Abstract translation: 高灵敏度SPR(表面等离子体共振)传感器至少包括具有顺序地形成有金属层和金属纳米粒子层的第一表面的棱镜。 光源通过棱镜的第二表面将入射光投影到棱镜中。 光被金属层和金属纳米颗粒层反射,并通过棱镜的第三表面离开棱镜。 光检测器检测反射光。 SPR传感器与传统传感器相比具有广泛的检测范围,适用于气体,化学物质和生物分子的检测。 此外,SPR传感器有利于一致地布置制造工艺,控制膜厚度,提高产品质量和降低制造成本。

    IC, circuitry, and RF BIST system
    72.
    发明授权
    IC, circuitry, and RF BIST system 有权
    IC,电路和RF BIST系统

    公开(公告)号:US09041421B2

    公开(公告)日:2015-05-26

    申请号:US13480969

    申请日:2012-05-25

    CPC classification number: G01R31/2822 G01R31/2884

    Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

    Abstract translation: 提供IC,电路和RF BIST系统。 RF BIST系统包括测试设备,模块电路和IC。 IC被布置为响应于来自测试设备的命令信号通过RF信号与模块电路通信,通过RF信号确定测试结果,并将测试结果报告给测试设备,其中模块电路是外部的 到IC和测试设备。

    Electrostatic discharge circuit using inductor-triggered silicon-controlled rectifier
    73.
    发明授权
    Electrostatic discharge circuit using inductor-triggered silicon-controlled rectifier 有权
    使用电感触发硅控整流器的静电放电电路

    公开(公告)号:US08952456B2

    公开(公告)日:2015-02-10

    申请号:US12711302

    申请日:2010-02-24

    CPC classification number: H01L27/0262

    Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

    Abstract translation: 代表性静电放电(ESD)保护电路包括可控硅整流器,其包括第一P型半导体材料,第一N型半导体材料,第二P型半导体材料和第二N型半导体材料的交替布置 电耦合在阳极和阴极之间的材料。 阳极电耦合到第一P型半导体材料,并且阴极电耦合到第二N型半导体材料。 ESD保护电路还包括电耦合在阳极和第二P型半导体材料之间或在阴极和第一N型半导体材料之间的电感器。

    Control circuit and control method for capacitive touch panel
    75.
    发明授权
    Control circuit and control method for capacitive touch panel 有权
    电容触摸屏的控制电路和控制方法

    公开(公告)号:US08884909B2

    公开(公告)日:2014-11-11

    申请号:US12379573

    申请日:2009-02-25

    CPC classification number: G06F3/044

    Abstract: A control circuit and a control method for a capacitive touch panel are provided. Therein, while a scanning signal charges and discharges each trace on the capacitive touch panel, a signal in phase with the scanning signal is provided to traces adjacent to the scanned trace or a ground layer under the scanned trace so as to lower parasitic capacitances between the scanned trace and the ground layer or other traces, thereby decreasing a base capacitance of the capacitive touch panel and enhancing a sensing result of the control circuit as well as providing a shielding effect and reducing noise interference so that the capacitive touch panel has improved performance.

    Abstract translation: 提供了一种用于电容式触摸面板的控制电路和控制方法。 其中,当扫描信号对电容式触摸面板上的每个迹线进行充电和放电时,将与扫描信号同相的信号提供给扫描迹线附近的迹线或扫描迹线下方的接地层,以便降低扫描信号之间的寄生电容 扫描轨迹和接地层或其他迹线,从而降低电容式触摸面板的基极电容并增强控制电路的感测结果,以及提供屏蔽效果并降低噪声干扰,使得电容式触摸面板具有改进的性能。

    Injection mold
    76.
    发明授权
    Injection mold 失效
    注塑模具

    公开(公告)号:US08262380B2

    公开(公告)日:2012-09-11

    申请号:US12821139

    申请日:2010-06-23

    CPC classification number: B29C33/304 B29C45/2606 B29L2011/0075

    Abstract: An exemplary injection mold for manufacturing a fiber optic connector includes a first mold, a second mold, an insert, two first positioning bar, and four second positioning bars. The first mold and the second mold cooperatively define a mold cavity. The mold cavity includes two lens molding recesses. The two inserts are attached to the second mold and located in the mold cavity. A dimension of each second bar in cross section is substantially smaller than that of each first positioning bar. One first positioning bar and two second positioning bars are arranged around each insert to position the insert, such that the inserts is suspended in the mold cavity and precisely aligns with the respective molding recesses.

    Abstract translation: 用于制造光纤连接器的示例性注射模具包括第一模具,第二模具,插入件,两个第一定位杆和四个第二定位杆。 第一模具和第二模具协同地限定模腔。 模腔包括两个透镜成型凹部。 两个插入件连接到第二模具并且位于模具腔中。 每个第二条横截面的尺寸基本上小于每个第一定位杆的尺寸。 一个第一定位杆和两个第二定位杆围绕每个插入件布置以定位插入件,使得插入件悬挂在模具腔中并且精确地对准相应的模制凹部。

    Apparatus for molding optical fiber connector
    77.
    发明授权
    Apparatus for molding optical fiber connector 失效
    光纤连接器成型设备

    公开(公告)号:US08246335B2

    公开(公告)日:2012-08-21

    申请号:US12976965

    申请日:2010-12-22

    Applicant: Chun-Yu Lin

    Inventor: Chun-Yu Lin

    CPC classification number: B29C45/14

    Abstract: An apparatus for molding optical fiber connector is provided. The optical fiber connector includes a main body. The main body has a blind hole for receiving an optical fiber two opposite surfaces being substantially parallel with the blind hole, and a lens portion aligned with the blind hole. The apparatus comprises a molding cavity and an insert for forming the blind hole. The molding cavity includes a central portion for forming the main body, a lens-forming portion for forming the lens portion, and two lateral portions for forming the corresponding surfaces. The molding cavity includes a first gate and a second gate for introducing molding material into the molding cavity. The first gate is located between the insert and one of the two lateral portions and the second gate is defined between the insert and the other one of the lateral potions.

    Abstract translation: 提供了一种用于模制光纤连接器的设备。 光纤连接器包括主体。 主体具有盲孔,用于接收与盲孔大致平行的两个相对表面的光纤,以及与盲孔对准的透镜部。 该装置包括模制腔和用于形成盲孔的插入件。 成型腔包括用于形成主体的中心部分,用于形成透镜部分的透镜形成部分和用于形成相应表面的两个侧部。 模制腔包括用于将模制材料引入模腔中的第一浇口和第二浇口。 第一门位于插入件和两个侧面部分中的一个之间,并且第二门限定在插入件和另一侧面部件之间。

    ESD PROTECTION FOR RF CIRCUITS
    78.
    发明申请
    ESD PROTECTION FOR RF CIRCUITS 有权
    射频电路的ESD保护

    公开(公告)号:US20120099228A1

    公开(公告)日:2012-04-26

    申请号:US12908064

    申请日:2010-10-20

    Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

    Abstract translation: 适用于射频(RF)装置的静电放电(ESD)电路,其包括耦合在VDD电源轨和VSS电源轨之间并具有RF I / O焊盘的RF电路,包括耦合在 VDD电源轨节点和VSS电源轨节点以及耦合在VDD电源轨节点和VSS电源轨节点之间以及RF I / O焊盘的LC槽结构。 LC槽结构包括VDD电源轨节点和RF I / O焊盘之间的第一个ESD模块,以及VSS电源轨节点和RF I / O焊盘之间的第二个ESD模块。 第一和第二ESD块中的至少一个包括彼此并联耦合的一对二极管和与一对二极管中的一个串联耦合的电感器。

    Integrated circuit with built-in self test circuit
    79.
    发明授权
    Integrated circuit with built-in self test circuit 有权
    集成电路内置自检电路

    公开(公告)号:US07969168B1

    公开(公告)日:2011-06-28

    申请号:US12137029

    申请日:2008-06-11

    CPC classification number: G01R31/3167 G01R31/3187

    Abstract: An embodiment of the invention provides an integrated circuit. The integrated circuit has an analog device-under-test (DUT), a memory receiving and storing a test program and a processor. The processor tests the analog DUT and outputs a test result in digital format by executing the test program, wherein the test result indicates whether the analog DUT workable according to a specification.

    Abstract translation: 本发明的实施例提供一种集成电路。 集成电路具有模拟器件测试(DUT),存储器接收和存储测试程序和处理器。 处理器测试模拟DUT并通过执行测试程序输出数字格式的测试结果,其中测试结果指示模拟DUT是否可以根据规范工作。

    HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS
    80.
    发明申请
    HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS 有权
    低电压CMOS工艺制造的低漏电流高耐压ESD钳位电路

    公开(公告)号:US20110149449A1

    公开(公告)日:2011-06-23

    申请号:US12641037

    申请日:2009-12-17

    CPC classification number: H01L27/0262

    Abstract: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.

    Abstract translation: 提供了一种静电放电(ESD)钳位电路,其包括多个相同的模块电路。 第一模块电路的阳极耦合到ESD钳位电路的阴极。 每个其他模块电路的阳极耦合到先前模块电路的阴极。 最后一个模块电路的阴极耦合到ESD钳位电路的接地端。 每个模块电路包括导通路径和检测电路。 检测电路耦合到阳极,阴极和模块电路的传导路径。 当模块电路的阳极电压的上升速度超过阈值时,检测电路使导通路径导通。

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