Abstract:
An array is formed with a protective cover on a substrate. The protective cover is patterned to produce an array of openings to the substrate. Desired material is deposited on the substrate through the openings. The protective cover may then be removed. In one embodiment, the protective cover is a conformal polymer, such as di-para-xylylene. It may be removed by mechanical peeling. The material may be biological material such as DNA. The protective cover may be used to prevent non-specific hybridization in inter-spot regions by performing hybridization with the cover still in place. Hybridization that occurs in such regions between the spots may be removed with removal of the protective cover.
Abstract:
An automatic voltage-identifying power supply device has a control module, a voltage regulation circuit, a current load measuring circuit electrically connected with an external post-stage power-receiving device, a power supply circuit and a pre-stage power supply device. After the post-stage power-receiving device is electrically connected with the current load measuring circuit, the control module can control the voltage regulation circuit to output a test voltage signal to the post-stage power-receiving device so that the test voltage signal is altered according to a preset sequence (e.g. progressively increasing) and the current load measuring circuit measures a response current signal of the post-stage power-receiving device corresponding to the test voltage signal. When a variation of the response current signal or a power variation is stable, the control module sets up the stable test voltage signal as an input voltage to the post-stage power-receiving device.
Abstract:
The present invention is directed to an isolated polypeptide containing SEQ ID NO: 1 or an immunogenic fragment thereof. Also disclosed is an isolated nucleic acid encoding the polypeptide or containing a sequence at least 70% identical to SEQ ID NO: 3. Within the scope of this invention are related expression vectors, host cells, and antibodies. Also disclosed are methods of producing the polypeptide, diagnosing coronavirus infection, and identifying a test compound for treating coronavirus infection.
Abstract translation:本发明涉及含有SEQ ID NO:1或其免疫原性片段的分离的多肽。 还公开了编码多肽的分离的核酸或含有与SEQ ID NO:3至少70%相同的序列。在本发明的范围内,是相关的表达载体,宿主细胞和抗体。 还公开了产生多肽的方法,诊断冠状病毒感染和鉴定用于治疗冠状病毒感染的测试化合物。
Abstract:
Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.
Abstract:
The invention provides a protection device for protecting a flat cable in an optical disk drive. The protection device includes a casing, whereon a main board is fixed inside the casing, and an opening is formed at a front edge of the casing. The protection device further includes a tray disposed inside the casing in a slidable manner, a circuit board disposed on a bottom of the tray, the flat cable connected to the main board and the circuit board, a cover disposed on the bottom of the tray, and a support frame connected to the cover and protruding towards a rear of the casing. The support frame is disposed on the bottom of the tray and adjacent to a position, where the flat cable is connected to the circuit board, for holding the flat cable and preventing the flat cable from dropping.
Abstract:
The invention provides novel immunogenic proteins LigA and LigB from Leptospira for use in the development of effective vaccines and antibodies, as well as improved diagnostic methods and kits.
Abstract:
This invention discloses a capacitive sensing device. The device includes a plurality of first conductive lines electrically isolated from each other; a plurality of second conductive lines electrically isolated from each other and electrically isolated from and stacked with the first conductive lines to form a plurality of intersecting points; and a plurality of electrical conductors electrically isolated from each other and correspondingly crossing the first and the second conductive lines and being around the intersecting points, wherein the first and second conductive lines and the electrical conductors are electrically isolated from each other. By doing so, when an electrical signal is driven to any first conductive lines, the first conductive lines is capacitively coupled to the second conductive lines with which it intersects, and the electrical conductors crossing the first conductive lines are respectively capacitively coupled to the first conductive lines and the second conductive lines which intersect with the first conductive lines to provide a higher compound capacitance.
Abstract:
A shock isolation structure applied in an optical disc drive is provided. The shock isolation structure includes a bottom portion, a top portion, and a neck portion jointing the bottom portion and the top portion. The portions have a through hole running through the top surface of the top portion and the bottom surface of the bottom portion along a run-through central line. In the neck portion, any ring-shaped cross section using the run-through central line as the normal has a first wall thickness on a first extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section, and has a second wall thickness on a second extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section. The first wall thickness is larger than the second wall thickness.
Abstract:
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
Abstract:
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.