AUTOMATIC VOLTAGE-IDENTIFYING POWER SUPPLY DEVICE AND METHOD THEREOF
    72.
    发明申请
    AUTOMATIC VOLTAGE-IDENTIFYING POWER SUPPLY DEVICE AND METHOD THEREOF 失效
    自动电压识别电源装置及其方法

    公开(公告)号:US20100176778A1

    公开(公告)日:2010-07-15

    申请号:US12651934

    申请日:2010-01-04

    CPC classification number: H02J7/0008 G01R19/0084 G01R31/40 H02S50/10

    Abstract: An automatic voltage-identifying power supply device has a control module, a voltage regulation circuit, a current load measuring circuit electrically connected with an external post-stage power-receiving device, a power supply circuit and a pre-stage power supply device. After the post-stage power-receiving device is electrically connected with the current load measuring circuit, the control module can control the voltage regulation circuit to output a test voltage signal to the post-stage power-receiving device so that the test voltage signal is altered according to a preset sequence (e.g. progressively increasing) and the current load measuring circuit measures a response current signal of the post-stage power-receiving device corresponding to the test voltage signal. When a variation of the response current signal or a power variation is stable, the control module sets up the stable test voltage signal as an input voltage to the post-stage power-receiving device.

    Abstract translation: 自动电压识别电源装置具有控制模块,电压调节电路,与外部后级电力接收装置电连接的电流负载测量电路,电源电路和前级电源装置。 在后级受电装置与当前的负载测量电路电连接之后,控制模块可以控制电压调节电路,将测试电压信号输出到后级电力接收装置,使得测试电压信号为 根据预设顺序(例如逐渐增加)改变,并且当前负载测量电路测量对应于测试电压信号的后级电力接收装置的响应电流信号。 当响应电流信号或功率变化的变化稳定时,控制模块将稳定的测试电压信号设置为后级接收电源的输入电压。

    Viral protein
    73.
    发明授权
    Viral protein 失效
    病毒蛋白

    公开(公告)号:US07691390B2

    公开(公告)日:2010-04-06

    申请号:US11857961

    申请日:2007-09-19

    Abstract: The present invention is directed to an isolated polypeptide containing SEQ ID NO: 1 or an immunogenic fragment thereof. Also disclosed is an isolated nucleic acid encoding the polypeptide or containing a sequence at least 70% identical to SEQ ID NO: 3. Within the scope of this invention are related expression vectors, host cells, and antibodies. Also disclosed are methods of producing the polypeptide, diagnosing coronavirus infection, and identifying a test compound for treating coronavirus infection.

    Abstract translation: 本发明涉及含有SEQ ID NO:1或其免疫原性片段的分离的多肽。 还公开了编码多肽的分离的核酸或含有与SEQ ID NO:3至少70%相同的序列。在本发明的范围内,是相关的表达载体,宿主细胞和抗体。 还公开了产生多肽的方法,诊断冠状病毒感染和鉴定用于治疗冠状病毒感染的测试化合物。

    IMAGE PROCESSING SYSTEM WITH A 4-T PIXEL AND METHOD THEREOF CAPABLE OF REDUCING FIXED PATTERN NOISE
    74.
    发明申请
    IMAGE PROCESSING SYSTEM WITH A 4-T PIXEL AND METHOD THEREOF CAPABLE OF REDUCING FIXED PATTERN NOISE 有权
    具有4-T像素的图像处理系统及其可减少固定图案噪声的方法

    公开(公告)号:US20100073525A1

    公开(公告)日:2010-03-25

    申请号:US12237403

    申请日:2008-09-25

    CPC classification number: H04N5/3742 H04N5/365 H04N5/378

    Abstract: Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

    Abstract translation: 提出了一种用于降低具有4-T(4晶体管)像素的图像处理系统中的固定模式噪声的电路及其方法。 图像处理系统包括两个电压源,两个电流源,4-T像素,线性化源极跟随器的第二部分,乒乓存储器,PGA和自动归零电路。 通过将自动归零电路耦合到PGA,形成开环,以在复位PGA时将PGA的运算放大器的输出钳位到稳定的参考电压,以便去除运放的输出端子处的直流偏移。

    PROTECTION DEVICE FOR PROTECTING A FLAT CABLE
    75.
    发明申请
    PROTECTION DEVICE FOR PROTECTING A FLAT CABLE 失效
    用于保护平板电缆的保护装置

    公开(公告)号:US20100032203A1

    公开(公告)日:2010-02-11

    申请号:US12432756

    申请日:2009-04-30

    CPC classification number: G11B33/122

    Abstract: The invention provides a protection device for protecting a flat cable in an optical disk drive. The protection device includes a casing, whereon a main board is fixed inside the casing, and an opening is formed at a front edge of the casing. The protection device further includes a tray disposed inside the casing in a slidable manner, a circuit board disposed on a bottom of the tray, the flat cable connected to the main board and the circuit board, a cover disposed on the bottom of the tray, and a support frame connected to the cover and protruding towards a rear of the casing. The support frame is disposed on the bottom of the tray and adjacent to a position, where the flat cable is connected to the circuit board, for holding the flat cable and preventing the flat cable from dropping.

    Abstract translation: 本发明提供一种用于保护光盘驱动器中的扁平电缆的保护装置。 保护装置包括壳体,其中主板固定在壳体内,并且在壳体的前边缘处形成开口。 保护装置还包括以滑动方式设置在壳体内的托盘,设置在托盘的底部的电路板,连接到主板和电路板的扁平电缆,设置在托盘底部的盖子, 以及支撑框架,其连接到所述盖并朝向所述壳体的后部突出。 支撑框架设置在托盘的底部并且靠近一个位置,扁平电缆连接到电路板上,用于保持扁平电缆并防止扁平电缆掉落。

    METHOD AND DEVICE FOR CAPACITIVE SENSING
    77.
    发明申请
    METHOD AND DEVICE FOR CAPACITIVE SENSING 有权
    用于电容感测的方法和装置

    公开(公告)号:US20100007630A1

    公开(公告)日:2010-01-14

    申请号:US12499981

    申请日:2009-07-09

    Applicant: CHIN-FU CHANG

    Inventor: CHIN-FU CHANG

    Abstract: This invention discloses a capacitive sensing device. The device includes a plurality of first conductive lines electrically isolated from each other; a plurality of second conductive lines electrically isolated from each other and electrically isolated from and stacked with the first conductive lines to form a plurality of intersecting points; and a plurality of electrical conductors electrically isolated from each other and correspondingly crossing the first and the second conductive lines and being around the intersecting points, wherein the first and second conductive lines and the electrical conductors are electrically isolated from each other. By doing so, when an electrical signal is driven to any first conductive lines, the first conductive lines is capacitively coupled to the second conductive lines with which it intersects, and the electrical conductors crossing the first conductive lines are respectively capacitively coupled to the first conductive lines and the second conductive lines which intersect with the first conductive lines to provide a higher compound capacitance.

    Abstract translation: 本发明公开了一种电容式感测装置。 该装置包括彼此电隔离的多个第一导电线; 多个彼此电隔离并与第一导电线电隔离并与其堆叠的第二导线,以形成多个相交点; 以及多个电导体,其彼此电隔离并且相应地穿过所述第一和所述第二导电线并且在所述交叉点附近,其中所述第一和第二导线和所述电导体彼此电隔离。 通过这样做,当电信号被驱动到任何第一导线时,第一导线与其相交的第二导线电容耦合,并且与第一导线交叉的电导体分别电容耦合到第一导电 线和与第一导线相交的第二导线以提供更高的复合电容。

    Shock isolation structure applied in optical disc drive
    78.
    发明授权
    Shock isolation structure applied in optical disc drive 失效
    冲击隔离结构应用于光盘驱动器

    公开(公告)号:US07636926B2

    公开(公告)日:2009-12-22

    申请号:US11157831

    申请日:2005-06-22

    CPC classification number: G11B33/08

    Abstract: A shock isolation structure applied in an optical disc drive is provided. The shock isolation structure includes a bottom portion, a top portion, and a neck portion jointing the bottom portion and the top portion. The portions have a through hole running through the top surface of the top portion and the bottom surface of the bottom portion along a run-through central line. In the neck portion, any ring-shaped cross section using the run-through central line as the normal has a first wall thickness on a first extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section, and has a second wall thickness on a second extension line starting from the run-through central line and extending towards the outer peripheral of the ring-shaped cross section. The first wall thickness is larger than the second wall thickness.

    Abstract translation: 提供了应用于光盘驱动器中的防震结构。 冲击隔离结构包括底部,顶部和连接底部和顶部的颈部。 这些部分具有穿过顶部的顶表面和底部的底表面沿着贯穿中心线延伸的通孔。 在颈部中,使用贯穿中心线作为法线的任何环形横截面在第一延伸线上具有从穿过中心线开始并朝向环形的外周延伸的第一壁厚 并且在第二延伸线上具有从穿过中心线开始并朝向环形横截面的外周边延伸的第二壁厚。 第一壁厚大于第二壁厚。

    Nonvolatile memory with a unified cell structure
    79.
    发明授权
    Nonvolatile memory with a unified cell structure 有权
    具有统一单元结构的非易失性存储器

    公开(公告)号:US07636252B2

    公开(公告)日:2009-12-22

    申请号:US11483241

    申请日:2006-07-07

    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

    Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元,解码器和布局方案,以消除单元阵列中的面积消耗的划分三阱,并允许字节擦除和字节程序用于高P / E周期。 此外,用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成,从而实现了优异的组合,单片,非易失性存储器。 与所有以前的技术不同,ROM,EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的,完全兼容的,高度可扩展的BN +单元和统一过程组成。 此外,其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小(以字节,页面和块为单位)以低成本的市场的需求。

    Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS
    80.
    发明申请
    Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS 失效
    行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面,扇区和芯片单元中的擦除

    公开(公告)号:US20090310411A1

    公开(公告)日:2009-12-17

    申请号:US12455936

    申请日:2009-06-09

    CPC classification number: G11C8/12 G11C16/0416 G11C16/08 G11C16/12 G11C16/16

    Abstract: An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

    Abstract translation: 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页,块,扇区或整个阵列的增量擦除阵列,同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路,用于选择非易失性存储单元以提供用于读取,编程,验证和擦除所选择的非易失性存储单元的偏置条件,同时最小化操作干扰并防止门外围设备中的故障。

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