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95 条记录 (耗时 0.028 秒)

    Air Isolation In High Density Non-Volatile Memory
    75.
    发明申请
    Air Isolation In High Density Non-Volatile Memory 有权
    高密度非易失性存储器中的空气隔离

    公开(公告)号：US20120178235A1

    公开(公告)日：2012-07-12

    申请号：US13348619

    申请日：2012-01-11

    申请人： Jayavel Pachamuthu ,  Vinod R. Purayath ,  George Matamis

    发明人： Jayavel Pachamuthu ,  Vinod R. Purayath ,  George Matamis

    IPC分类号： H01L21/764

    CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

    摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

    摘要翻译： 提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。 至少部分地在衬底的有源区域之间的隔离区域中形成气隙。 气隙可以在相邻层堆叠柱之间的衬底表面之上进一步延伸。 至少部分地在隔离区域中形成牺牲材料，随后形成电介质衬垫。 去除牺牲材料以在形成控制栅极层之前限定气隙，然后蚀刻它和层堆叠列以形成单独的控制栅极和非易失性存储元件的列。

    Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
    76.
    发明授权
    Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution 有权
    使用聚合物溶液形成包括自对准金属纳米点的浮栅的存储器的方法

    公开(公告)号：US08193055B1

    公开(公告)日：2012-06-05

    申请号：US11958875

    申请日：2007-12-18

    申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

    发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai ,  Tuan D. Pham

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/11521 ,  H01L29/42332 ,  Y10S977/72 ,  Y10S977/81

    摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

    摘要翻译： 提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。 在一个示例性方法中，将金属盐离子加入到共聚物溶液的芯中。 金属盐还原导致金属原子在芯中聚集，形成金属纳米点。 使用旋涂或浸涂将共聚物溶液施加到基板上的栅极氧化物上。 由于共聚物构型，纳米点被保持在栅极氧化物上的均匀的2D栅格中。 选择聚合物以在纳米点之间提供期望的纳米尺寸和间隔。 聚合物固化和去除过程使栅极氧化物上的纳米点离开。 在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
    77.
    发明申请
    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
    具有扁平单元结构和空气间隙隔离的非易失性存储器

    公开(公告)号：US20110309430A1

    公开(公告)日：2011-12-22

    申请号：US13162550

    申请日：2011-06-16

    申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L29/788 ,  H01L21/764

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

    摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

    摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

    Methods of using single spacer to triple line/space frequency
    79.
    发明授权
    Methods of using single spacer to triple line/space frequency 有权
    使用单间隔线三线/空间频率的方法

    公开(公告)号：US07871909B1

    公开(公告)日：2011-01-18

    申请号：US12689677

    申请日：2010-01-19

    申请人： Chun-Ming Wang ,  Chen-Che Huang ,  Masaaki Higashitani ,  George Matamis

    发明人： Chun-Ming Wang ,  Chen-Che Huang ,  Masaaki Higashitani ,  George Matamis

    IPC分类号： H01L21/3205 ,  H01L21/44

    CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11517 ,  Y10S438/947

    摘要： Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ⅓ the width of lines in the first pattern.

    摘要翻译： 公开了仅使用单个间隔物形成具有三倍于第一图案的线频率的图案的方法。 例如，使用光刻工艺在第一和第二材料中形成第一图案。 侧壁间隔件由与第二材料中的特征的暴露的侧壁相邻的第三材料形成。 第一材料中第一图案中的特征的宽度减小。 例如，以最终图案将宽度减小到大约特征的目标宽度。 使用第一材料的剩余部分作为掩模来减少第二材料中的第一图案中的特征的宽度。 基于第二材料和侧壁间隔物的剩余部分形成第二图案。 第二图案中的特征可以是具有第一图案中的线的宽度的大约1/3的线。

    Spacer Patterns Using Assist Layer For High Density Semiconductor Devices
    80.
    发明申请
    Spacer Patterns Using Assist Layer For High Density Semiconductor Devices 有权
    使用高密度半导体器件辅助层的间隔图

    公开(公告)号：US20100240182A1

    公开(公告)日：2010-09-23

    申请号：US12791103

    申请日：2010-06-01

    申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

    发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

    摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小光刻可分辨元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。