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    Semiconductor memory device and magneto-logic circuit
    71.
    发明授权
    Semiconductor memory device and magneto-logic circuit 有权
    半导体存储器件和磁逻辑电路

    公开(公告)号：US07755930B2

    公开(公告)日：2010-07-13

    申请号：US11976007

    申请日：2007-10-19

    申请人： Kee-won Kim ,  Young-jin Cho ,  Hyung-soon Shin ,  Sung-hoon Choa ,  Seung-jun Lee ,  In-jun Hwang

    发明人： Kee-won Kim ,  Young-jin Cho ,  Hyung-soon Shin ,  Sung-hoon Choa ,  Seung-jun Lee ,  In-jun Hwang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

    摘要： Provided are a semiconductor memory device and a magneto-logic circuit which change the direction of a magnetically induced current according to a logical combination of logic states of a plurality of input values. The semiconductor memory device comprises a current driving circuit, a magnetic induction layer, and a resistance-variable element. The current driving circuit receives a plurality of input values and changes the direction of a magnetically induced current according to a logical combination of logic states of the input values. The magnetic induction layer induces magnetism having a direction varying according to the direction of the magnetically induced current. The resistance-variable element has a resistance varying according to the direction of the magnetism induced by the magnetic induction layer.

    摘要翻译： 提供了根据多个输入值的逻辑状态的逻辑组合来改变磁感应电流的方向的半导体存储器件和磁电逻辑电路。 半导体存储器件包括电流驱动电路，磁感应层和电阻可变元件。 电流驱动电路根据输入值的逻辑状态的逻辑组合接收多个输入值并改变磁感应电流的方向。 磁感应层诱导具有根据磁感应电流的方向变化的方向的磁性。 电阻可变元件具有根据由磁感应层感应的磁性方向而变化的电阻。

    Semiconductor memory device including recessed control gate electrode
    72.
    发明授权
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US07732855B2

    公开(公告)日：2010-06-08

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L21/28

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Magnetic memory device and method
    73.
    发明授权
    Magnetic memory device and method 有权
    磁记忆装置及方法

    公开(公告)号：US07508699B2

    公开(公告)日：2009-03-24

    申请号：US11164579

    申请日：2005-11-29

    申请人： In-Jun Hwang ,  Tae-wan Kim ,  Won-cheol Jeong

    发明人： In-Jun Hwang ,  Tae-wan Kim ,  Won-cheol Jeong

    IPC分类号： G11C11/00

    CPC分类号： G11C11/15

    摘要： An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed.

    摘要翻译： 磁性随机存取存储器（MRAM）装置的示例性实施例包括具有自由层的磁性隧道结，具有覆盖自由层的表面的第一部分的第一电极（第一磁场产生装置）和电力 源极经由覆盖小于第一电极的第一部分的一半的连接而连接到第一电极。 MRAM器件的另一个示例性实施例包括磁性隧道结，直接连接到磁性隧道结相对侧上的磁性隧道结的第一和第二电极（第一和第二磁场产生装置）和具有一个极点的电源 经由第一连接器连接到第一电极，并且具有通过第二连接连接到第二电极的第二极，其中第一和第二连接部从第一和第二电极与磁性隧道结之间的连接侧向偏移。 还公开了操作和制造这些磁性随机存取存储器的方法。

    Multi-stack memory device
    75.
    发明申请
    Multi-stack memory device 有权
    多堆存储器件

    公开(公告)号：US20080137389A1

    公开(公告)日：2008-06-12

    申请号：US11978583

    申请日：2007-10-30

    申请人： In-Jun Hwang ,  Sung-hoon Choa ,  Young-Jin Cho ,  Kee-Won Kim

    发明人： In-Jun Hwang ,  Sung-hoon Choa ,  Young-Jin Cho ,  Kee-Won Kim

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C11/16 ,  G11C19/0808 ,  G11C2213/71 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： Provided is a multi-stack memory device that includes a storage unit group including a plurality of storage units that are vertically stacked and form a plurality of storage unit rows, and a plurality of transistors connected to the storage unit group, wherein the transistors that are connected to the storage units which are included in at least two rows of the plurality of the storage unit rows and are connected by a common wire. The common wire may be a gate line or a bit line.

    摘要翻译： 本发明提供一种多层存储装置，其特征在于，包括具有垂直堆叠的多个存储单元和多个存储单元行的存储单元组，以及与所述存储单元组连接的多个晶体管，其中， 连接到包含在多个存储单元行中的至少两行的存储单元，并通过公共线连接。 公共线可以是栅极线或位线。

    Method of manufacturing a multi-purpose magnetic film structure
    77.
    发明申请
    Method of manufacturing a multi-purpose magnetic film structure 有权
    制造多用途磁性膜结构的方法

    公开(公告)号：US20080009080A1

    公开(公告)日：2008-01-10

    申请号：US11898762

    申请日：2007-09-14

    申请人： Tae-wan Kim ,  Wan-jun Park ,  Sang-jin Park ,  In-jun Hwang ,  Soon-ju Kwon ,  Young-keun Kim ,  Richard Gambino

    发明人： Tae-wan Kim ,  Wan-jun Park ,  Sang-jin Park ,  In-jun Hwang ,  Soon-ju Kwon ,  Young-keun Kim ,  Richard Gambino

    IPC分类号： H01L21/00

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673

    摘要： Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions.

    摘要翻译： 提供了使用自旋电荷的多用途磁性膜结构，其制造方法，具有该自旋电荷的半导体器件，以及操作半导体存储器件的方法。 多用途磁性膜结构包括下部磁性膜，形成在下部磁性膜上的隧道膜和形成在隧道膜上的上部磁性膜，其中下部和上部磁性膜是形成其间电化学电位差的铁磁性膜 当上下磁性膜具有相反的磁化方向时。

    Non-linear characteristic correction apparatus and method therefor
    80.
    发明授权
    Non-linear characteristic correction apparatus and method therefor 失效
    非线性特征校正装置及其方法

    公开(公告)号：US6166781A

    公开(公告)日：2000-12-26

    申请号：US943982

    申请日：1997-10-03

    申请人： Mal-seob Kwak ,  Jun Sunwoo ,  In-jun Hwang ,  Bong-soon Kang

    发明人： Mal-seob Kwak ,  Jun Sunwoo ,  In-jun Hwang ,  Bong-soon Kang

    IPC分类号： H04N1/401 ,  H04N1/407 ,  H04N5/202 ,  H04N9/69 ,  G03F3/08

    CPC分类号： H04N1/407 ,  H04N1/401 ,  H04N5/202 ,  H04N9/69

    摘要： A non-linear response correction apparatus and method reduce look up table size and output error. In one embodiment, a range of an N-bit input signal is split into two or more sectors, based on a gradient of a non-linear correction curve and an allowable error, and then a N-bit input signal is divided into U upper bits and D lower bits where U and D depend on which sector contains the input signal. First and second look up tables read first and second data stored therein, respectively, using the upper bits of the digital signal as an address. The first data is the difference between a corrected signal and the input signal, and the second data is the gradient of the corrected signal with respect to the gradient of the input signal. The second data read from the second look up table is multiplied by the lower bits, and the first data read from the first look up table is added to the upper bits. The sum is added to the product to produce an N-bit digital corrected signal that compensates for the non-linear characteristics.

    摘要翻译： 非线性响应校正装置和方法减少了查找表的大小和输出错误。 在一个实施例中，N位输入信号的范围基于非线性校正曲线的梯度和容许误差被分成两个或更多个扇区，然后将N位输入信号分成U上限 位和D低位，其中U和D取决于哪个扇区包含输入信号。 第一和第二查询表使用数字信号的高位分别读取存储在其中的第一和第二数据作为地址。 第一数据是校正信号和输入信号之间的差，第二数据是相对于输入信号的梯度的校正信号的梯度。 将从第二查询表读取的第二数据乘以较低位，并将从第一查询表读取的第一数据添加到高位。 该总和被添加到产品中以产生补偿非线性特性的N位数字校正信号。