公开(公告)号：US08425048B1

公开(公告)日：2013-04-23

申请号：US13717413

申请日：2012-12-17

Applicant: Intersil Americas Inc.

Inventor： Daryl Chamberlin ,  Dong Zheng

IPC: G03B21/14 ,  H04N3/22

CPC classification number: H04N5/74 ,  G03B21/14 ,  G03B21/28 ,  H04N9/3129 ,  H04N9/3194

Abstract: Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed.

Abstract translation: 本发明的实施例通常涉及可用于检测光束未对准的电路，系统和方法，从而可以执行对这种不对准的补偿。 根据实施例，电路包括具有多个电隔离PD段的光检测器（PD）。 另外，该电路具有包括开关的电路，其被配置为控制指示由多个电隔离的PD段检测到的光的电流如何被算术组合。 当开关处于第一配置时，由电路产生的信号指示垂直光束对准。 当开关处于第二配置时，由电路产生的信号指示水平光束对准。 可以使用指示垂直光束对准和水平光束对准的信号来检测光束未对准，从而可以执行对这种未对准的补偿。

公开(公告)号：US20040174205A1

公开(公告)日：2004-09-09

申请号：US10379140

申请日：2003-03-04

Applicant: Intersil Americas Inc.

Inventor： Harold Allen Wittlinger

IPC: G05F001/10 ,  G05F003/02

CPC classification number: G05F3/262

Abstract: A voltage margin circuit has an input that receives a control voltage for programming an output reference voltage. The control voltage is coupled through an input resistor to an operational amplifier, referenced to a voltage midway between the voltage range of the input voltage and having its output coupled to a pair of transistors, whose current flow paths are coupled to inputs of a first pair of current mirrors. Outputs of the first current mirrors pair are cross-coupled to inputs of a second current mirrors pair. Outputs of the second current mirror pair are coupled through an output resistor to a prescribed voltage. The output reference voltage is the sum of the prescribed voltage and an offset as the product of the output resistor and an output current supplied by one of the third and fourth current mirrors.

Abstract translation: 电压余量电路具有接收用于编程输出参考电压的控制电压的输入。 控制电压通过输入电阻器耦合到运算放大器，参考输入电压的电压范围之间的中间电压，并且其输出耦合到一对晶体管，其电流流动路径耦合到第一对的输入 的电流镜。 第一电流镜对的输出交叉耦合到第二电流镜对的输入。 第二电流镜对的输出通过输出电阻器耦合到规定的电压。 输出参考电压是作为输出电阻和由第三和第四电流镜之一提供的输出电流的乘积的规定电压和偏移之和。

公开(公告)号：US20040164836A1

公开(公告)日：2004-08-26

申请号：US10786533

申请日：2004-02-26

Applicant: Intersil Americas Inc.

Inventor： Xingwu Wang ,  Chungsheng Yang

IPC: H01F005/00

CPC classification number: H01F41/046 ,  H01F17/0006 ,  H01F17/06 ,  Y10T29/4902

Abstract: The present invention relates to inductors with improved inductance and quality factor. In one embodiment, a magnetic thin film inductor is disclosed. In this embodiment, magnetic thin film inductor includes a plurality of elongated conducting regions and magnetic material. The plurality of elongated conducting regions are positioned parallel with each other and at a predetermined spaced distance apart from each other. The magnetic material encases the plurality of conducting regions, wherein when currents are applied to the conductors, current paths in each of the conductors cause the currents to generally flow in the same direction thereby enhancing mutual inductance.

公开(公告)号：US20040159912A1

公开(公告)日：2004-08-19

申请号：US10366158

申请日：2003-02-13

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L027/082

CPC classification number: H01L29/7304 ,  H01L27/0658 ,  H01L27/067

Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.

Abstract translation: 公开了一种集成电路，其包括具有改进的向前二次击穿的双极晶体管。 在一个实施例中，双极晶体管包括基极，集电极，耦合到公共发射极的多个发射极部分和用于每个发射极部分的镇流发射极。 每个镇流电阻器耦合在公共发射极和相关的发射极部分之间。 选择每个镇流电阻器的尺寸，使得镇流电阻器的尺寸相对于双极晶体管的侧表面在二维方向上变化。

公开(公告)号：US20040146101A1

公开(公告)日：2004-07-29

申请号：US10350599

申请日：2003-01-24

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce

IPC: H03K007/08 ,  H03K009/08

CPC classification number: H03K5/133 ,  H02M3/157 ,  H03K7/08 ,  H03K2005/00058 ,  H03L7/00

Abstract: A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter's DC output voltage.

Abstract translation: 数字实现的脉冲宽度调制（PWM）信号发生器基于PWM参考时钟的全周期形成PWM脉冲宽度作为有理数，并提供与多相DC-DC相兼容的PWM脉冲信号的非常高的有效分辨率， DC转换器。 完全数字化允许数字错误累积和校正发生在PWM信号的原点，在相对较慢的电压控制反馈回路的上游。 量化误差在它们可以在转换器的直流输出电压中积累之前被校正。

公开(公告)号：US20040145360A1

公开(公告)日：2004-07-29

申请号：US10350755

申请日：2003-01-24

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  Nicolaas W. Van Vonno

IPC: G05F001/40

CPC classification number: H02J1/102 ,  H02M3/1584

Abstract: An electronic device may include a circuit board, at least one load circuit carried by the circuit board, and a power distribution conductor carried by the circuit board and connected to the at least one load circuit. The electronic device may also include a multiphase switching regulator including a plurality of output stages connected to the power distribution conductor, and a controller for controlling the output stages based upon respective phase currents. The respective phase currents may be derived from corresponding voltage drops across the power distribution conductor and a matrix of resistivity values.

Abstract translation: 电子设备可以包括电路板，由电路板承载的至少一个负载电路和由电路板承载并连接到至少一个负载电路的配电导体。 电子设备还可以包括多相开关调节器，其包括连接到配电导体的多个输出级，以及用于基于各自的相电流来控制输出级的控制器。 相应的相电流可以从功率分布导体上的相应电压降和电阻率值矩阵导出。

公开(公告)号：US20040125968A1

公开(公告)日：2004-07-01

申请号：US10738590

申请日：2003-12-15

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  Donald F. Hemmenway

IPC: H04R003/00 ,  H03F021/00

CPC classification number: H01L21/8234 ,  H01L21/8249 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7815 ,  H03F1/523 ,  H03F3/187 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/72

Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the Nnull buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.

Abstract translation: 单体1.75安装在扬声器箱1.71中以驱动扬声器1.70的音圈1.74。 单片集成电路可以是D类放大器1.10，并且是至少一个半桥或全桥功率MOSFET器件。 公开了用于形成桥式驱动器电路的mos开关器件2.20的结构和工艺。 还公开了桥接电路的QVDMOS晶体管4.43的N +掩埋层4.14。

公开(公告)号：US20040070382A1

公开(公告)日：2004-04-15

申请号：US10673684

申请日：2003-09-29

Applicant: Intersil Americas Inc.

Inventor： Michael M. Walters ,  Xuening Li ,  Thomas A. Jochum

IPC: G05F001/40

CPC classification number: H02J1/102 ,  H02M3/156 ,  H02M3/1584

Abstract: A multiphase ripple voltage regulator generator employs a hysteretic comparator referenced to upper and lower voltage thresholds. The hysteretic comparator monitors a master ripple voltage waveform developed across a capacitor supplied with a current proportional to the difference between the output voltage and either the input voltage or ground. The output of the hysteretic comparator generates a master clock signal that is sequentially coupled to PWM latches, the states of which define the durations of respective components of the synthesized ripple voltage. A respective PWM latch has a first state initiated by a selected master clock signal and terminated by an associated phase voltage comparator that monitors a respective phase node voltage.

Abstract translation: 多相纹波电压调节器采用基于上限和下限电压阈值的滞后比较器。 迟滞比较器监视在电容器上产生的主纹波电压波形，其电流与输出电压和输入电压或地之间的差成比例。 迟滞比较器的输出产生顺序耦合到PWM锁存器的主时钟信号，其状态限定合成纹波电压的各个分量的持续时间。 相应的PWM锁存器具有由所选择的主时钟信号启动的第一状态，并且由相关联的相位电压比较器终止，监视相应的相位节点电压。

公开(公告)号：US20030222706A1

公开(公告)日：2003-12-04

申请号：US10161516

申请日：2002-06-03

Applicant: Intersil Americas Inc.

Inventor： Leonel E. Enriquez ,  Douglas L. Youngblood

IPC: G05F001/10

CPC classification number: G05F3/30

Abstract: A bandgap reference-based voltage and current generator has a distributed circuit architecture, to reduce the number of voltage dropping components between voltage supply rails containing bandgap voltage generator circuitry. Base current error compensation circuitry is incorporated into current mirror circuits of the generator to yield a composite current having a desired component, defined exclusively in accordance with the desired bandgap voltage, and a base error component containing the desired bandgap voltage, but modified by a second base current error. By differentially combining these two components, the multiple port output current mirror stage removes the base error component of the composite current, leaving only the desired bandgap-based component at each of plural precision output current ports.

Abstract translation: 基于带隙参考的电压和电流发生器具有分布式电路架构，以减少包含带隙电压发生器电路的电压轨之间的降压组件的数量。 基极电流误差补偿电路被并入到发电机的电流镜像电路中，以产生具有根据期望的带隙电压专门定义的期望分量的复合电流，以及包含期望的带隙电压的基本误差分量，但是由第二 基准电流误差。 通过差分组合这两个组件，多端口输出电流镜级除去复合电流的基本误差分量，在多个精密输出电流端口中仅留下所需的基于带隙的分量。

公开(公告)号：US20030201761A1

公开(公告)日：2003-10-30

申请号：US10357924

申请日：2003-02-04

Applicant: Intersil Americas Inc., State of Incorporation: Delaware

Inventor： Matthew B. Harris

IPC: G05F001/40

CPC classification number: H02J1/102 ,  H02M3/1584

Abstract: A multi-phase DC-DC converter architecture in which parameters including error signal gains and modulator gains are defined so as to balance multiple converter channel currents, irrespective of whether the converter channels are supplied with the same or different input voltages.

Abstract translation: 定义了包括误差信号增益和调制器增益的参数以便平衡多个转换器通道电流的多相DC-DC转换器架构，而不管转换器通道是否具有相同或不同的输入电压。