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    Display device and method of manufacturing the same
    71.
    发明授权
    Display device and method of manufacturing the same 有权
    显示装置及其制造方法

    公开(公告)号：US08045112B2

    公开(公告)日：2011-10-25

    申请号：US12147720

    申请日：2008-06-27

    Applicant: Jun-woo Lee ,  Hwa-sung Woo ,  Baek-kyun Jeon ,  Ji-won Sohn ,  In-suk Lee ,  Kyoung-tae Kim

    Inventor： Jun-woo Lee ,  Hwa-sung Woo ,  Baek-kyun Jeon ,  Ji-won Sohn ,  In-suk Lee ,  Kyoung-tae Kim

    IPC: G02F1/1333

    CPC classification number: G02F1/133707 ,  G02F2001/133742 ,  G02F2001/134345

    Abstract: A display device includes: a first panel having a pixel region including a pixel electrode therein; a second panel having a common electrode facing the first panel; a liquid crystal layer having vertically aligned liquid crystal molecules interposed between the first and second panels; a first alignment layer disposed on the pixel electrode; and a second alignment layer disposed on the common electrode. At least one of the pixel electrode and the common electrode has a micro slit pattern. At least one of the first and second alignment layers divides the pixel region into domains, is formed to have pretilt directions corresponding to a given domain, and pretilts the vertically aligned liquid crystal molecules in the given domain. A direction of summed horizontal components of a fringe field at an edge of the pixel region is substantially equal to a direction of summed horizontal components of a pretilt direction of the at least one of the first and second alignment layer.

    Abstract translation: 一种显示装置，包括：第一面板，具有包括像素电极的像素区域; 具有面向所述第一面板的公共电极的第二面板; 具有插入在第一和第二面板之间的垂直排列的液晶分子的液晶层; 设置在像素电极上的第一取向层; 以及设置在公共电极上的第二取向层。 像素电极和公共电极中的至少一个具有微狭缝图案。 第一和第二对准层中的至少一个将像素区域划分成区域，形成为具有对应于给定域的预倾斜方向，并且预倾斜给定域中的垂直取向的液晶分子。 像素区域的边缘处的边缘场的相加的水平分量的方向基本上等于第一和第二取向层中的至少一个的预倾斜方向的相加的水平分量的方向。

    INTERNAL VOLTAGE GENERATOR
    72.
    发明申请
    INTERNAL VOLTAGE GENERATOR 有权
    内部电压发生器

    公开(公告)号：US20110140768A1

    公开(公告)日：2011-06-16

    申请号：US12647875

    申请日：2009-12-28

    Applicant: Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

    Inventor： Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

    IPC: G05F1/10

    CPC classification number: G05F1/56

    Abstract: An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

    Abstract translation: 内部电压发生器包括：检测单元，被配置为与参考电压相比检测内部电压的电平; 第一驱动单元，被配置为响应于所述检测单元的输出信号，对输出所述内部电压的内部电压端子进行放电; 电流检测单元，被配置为检测流过所述第一驱动单元的放电电流; 以及第二驱动单元，其被配置为响应于所述电流检测单元的输出信号对所述内部电压端子进行充电。

    SEMICONDUCTOR MEMORY APPARATUS
    73.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS 失效
    半导体存储器

    公开(公告)号：US20100157643A1

    公开(公告)日：2010-06-24

    申请号：US12495026

    申请日：2009-06-30

    Applicant: Jun Woo Lee

    Inventor： Jun Woo Lee

    IPC: G11C5/02 ,  G11C7/00

    CPC classification number: G11C7/1048

    Abstract: A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first data line and a second data line at a predetermined distance, respectively, which are parallel with each other and the most adjacent to each other and the non-inversion repeater or the inversion repeater is arranged at first positions corresponding to the first data line and the second data line, respectively. The non-inversion repeaters are arranged on one of the first data line and the second data line while the inversion repeaters are arranged on the other first data line and the second data line, at second positions except for the first arrangement positions of positions corresponding to the first data line and the second data line, respectively.

    Abstract translation: 半导体存储装置包括不反转数据并输出反相数据的非反转中继器; 反转中继器，反转数据并输出反相数据。 非反转中继器或反转中继器分别布置在彼此平行并且彼此最相邻且非相邻中继器或反演的预定距离的第一数据线和第二数据线上 中继器分别布置在与第一数据线和第二数据线对应的第一位置处。 非反转中继器被布置在第一数据线和第二数据线中的一个上，而反转中继器被布置在另一第一数据线和第二数据线上的第二位置处，除了对应于 第一数据线和第二数据线。

    DATA OUTPUT CIRCUIT
    75.
    发明申请
    DATA OUTPUT CIRCUIT 有权
    数据输出电路

    公开(公告)号：US20100061157A1

    公开(公告)日：2010-03-11

    申请号：US12327397

    申请日：2008-12-03

    Applicant: Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

    Inventor： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

    IPC: G11C7/00 ,  G11C8/18 ,  G11C5/14

    CPC classification number: G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

    Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

    Abstract translation: 数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据 数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

    LATCH CIRCUIT
    77.
    发明申请
    LATCH CIRCUIT 审中-公开
    锁定电路

    公开(公告)号：US20100013535A1

    公开(公告)日：2010-01-21

    申请号：US12344642

    申请日：2008-12-29

    Applicant: Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

    Inventor： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

    IPC: H03K3/00

    CPC classification number: H03K3/356139 ,  H03K21/023

    Abstract: A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock.

    Abstract translation: 锁存电路包括：数据输入/输出单元，被配置为响应于输入数据形成通过第一节点的电流路径以输出输出数据;保持单元，被配置为响应于输出形成通过第二节点的电流路径 用于存储输出数据的数据，以及响应于时钟并行耦合到第一和第二节点的时钟输入单元。

    SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR
    79.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR 失效
    包括相位检测器的半导体器件

    公开(公告)号：US20090278577A1

    公开(公告)日：2009-11-12

    申请号：US12164758

    申请日：2008-06-30

    Applicant: Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

    Inventor： Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03K3/356121 ,  H03K3/356182

    Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

    Abstract translation: 一种半导体器件，包括边沿同步器，其输出通过使选通信号的转变时间点与主时钟或子时钟的时钟沿同步而产生的同步选通信号;输出相位确定信号的检测器， 主时钟和子时钟响应于同步选通信号;以及占空比校正器，其响应于相位确定信号调整主时钟和子时钟的占空比。

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