公开(公告)号：US20120092926A1

公开(公告)日：2012-04-19

申请号：US13272601

申请日：2011-10-13

申请人： Sung Jin WHANG ,  Kwon Hong ,  Ki Hong Lee

发明人： Sung Jin WHANG ,  Kwon Hong ,  Ki Hong Lee

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

摘要： A three dimensional non-volatile memory structure according to an aspect of this disclosure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.

摘要翻译： 根据本公开的一个方面的三维非易失性存储器结构包括多个层间介电层和交替层叠在衬底上的多个控制栅极，形成为穿透多个层间电介质层的沟道和多个控制 栅极，形成为围绕所述沟道的隧道绝缘层，设置在所述多个层间电介质层和所述隧道绝缘层之间的多个浮动栅极，其中所述多个浮置栅极的厚度大于所述层间电介质 层，以及设置在多个控制栅极和多个浮置栅极之间的电荷阻挡层。

公开(公告)号：US20120021574A1

公开(公告)日：2012-01-26

申请号：US13244247

申请日：2011-09-23

申请人： Ki-Hong LEE ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong LEE ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US20110266611A1

公开(公告)日：2011-11-03

申请号：US12981298

申请日：2010-12-29

申请人： Beom-Yong KIM ,  Ki-Hong LEE

发明人： Beom-Yong KIM ,  Ki-Hong LEE

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/7889 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7926

摘要： A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer.

摘要翻译： 非易失性存储器件包括多个层间电介质层和用于交替层叠在衬底上的栅电极的导电层，通过层间电介质层和导电层的通道沟槽和暴露衬底，电荷阻挡层和电荷陷阱或 形成在沟槽的侧壁上的电荷存储层，形成在电荷阱或电荷存储层的表面处的耦合防止层，以及形成在耦合防止层上的隧道绝缘层。

公开(公告)号：US20100317166A1

公开(公告)日：2010-12-16

申请号：US12493439

申请日：2009-06-29

申请人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US20100258852A1

公开(公告)日：2010-10-14

申请号：US12754395

申请日：2010-04-05

申请人： Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

发明人： Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

摘要翻译： 一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽 在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出 衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

公开(公告)号：US20100163963A1

公开(公告)日：2010-07-01

申请号：US12493820

申请日：2009-06-29

申请人： Ki-Hong LEE ,  Kwon HONG

发明人： Ki-Hong LEE ,  Kwon HONG

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

摘要： There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.

摘要翻译： 提供了一种非易失性存储器件，其具有在衬底上形成的隧道介电层，所述电荷俘获层形成在所述隧道介电层上并且包括至少一个电荷存储层和至少一个电荷俘获层，电荷阻挡层 形成在电荷捕获层上，以及形成在电荷阻挡层上的栅电极。

公开(公告)号：US20090108334A1

公开(公告)日：2009-04-30

申请号：US12164720

申请日：2008-06-30

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11568

摘要： A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The charge trapping layers are disposed on the active regions in island forms where the charge trapping layers are separated from each other in the first direction and disposed on the respective active regions between the isolation layers in a second direction perpendicular to the first direction. The blocking layer is disposed on the isolation layers and the charge trapping layers. The control gate electrode is disposed on the charge trapping layer.

摘要翻译： 电荷俘获装置包括多个隔离层，多个电荷俘获层，阻挡层和控制栅电极。 隔离层限定有源区，并且隔离层和有源区沿着半导体衬底上的第一方向作为相应条延伸。 电荷捕获层以岛形式设置在有源区，其中电荷捕获层在第一方向上彼此分离，并且在垂直于第一方向的第二方向上设置在隔离层之间的相应有源区上。 阻挡层设置在隔离层和电荷俘获层上。 控制栅电极设置在电荷捕获层上。