公开(公告)号：US20140042074A1

公开(公告)日：2014-02-13

申请号：US14113307

申请日：2012-04-26

Applicant: Jung-min Noh ,  Dae Joong Kim ,  Dong-eul Park ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Kwang-Jin Lee

Inventor： Jung-min Noh ,  Dae Joong Kim ,  Dong-eul Park ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Kwang-Jin Lee

IPC: B01D63/02

CPC classification number: B01D63/02 ,  B01D61/14 ,  B01D61/18 ,  B01D61/20 ,  B01D2311/20 ,  B01D2313/18 ,  B01D2313/24 ,  B01D2313/243 ,  B01D2315/06 ,  C02F1/444 ,  C02F2103/007 ,  C02F2103/42 ,  Y02W10/33 ,  Y02W10/37

Abstract: Disclosed is an energy-saving and eco-friendly filtration system which is capable of minimizing the amount of the energy required for the filtration, thereby remarkably reducing the cost of water treatment. The filtration system of the present invention comprises: a feed water tank for storing a feed water to be treated; a hollow fiber membrane module for filtering the feed water supplied from the feed water tank; and a filtrate tank for storing a filtrate produced by the hollow fiber membrane module, wherein the hollow fiber membrane module comprises a plurality of hollow fiber membranes for filtering the feed water, and the sum of head pressure of the feed water in the feed water tank and water pressure of the filtrate in accordance with siphon principle is higher than the threshold membrane pressure of the hollow fiber membranes.

Abstract translation: 公开了一种节能环保的过滤系统，其能够最小化过滤所需的能量的量，从而显着降低了水处理的成本。 本发明的过滤系统包括：用于储存待处理给水的给水箱; 用于过滤从给水箱供给的给水的中空纤维膜组件; 以及用于储存由中空纤维膜组件制成的滤液的滤液槽，其中中空纤维膜组件包括用于过滤给水的多个中空纤维膜，以及给水箱中的给水的头部压力之和 滤液的水压根据虹吸原理高于中空纤维膜的膜膜压力。

公开(公告)号：US20140027360A1

公开(公告)日：2014-01-30

申请号：US14004769

申请日：2012-03-16

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: B01D63/02

CPC classification number: B01D63/02 ,  B01D61/18 ,  B01D63/04 ,  B01D65/00 ,  B01D2313/06 ,  B01D2313/12 ,  B01D2313/20 ,  B01D2315/06 ,  C02F1/44

Abstract: Disclosed are a filtration apparatus having the advantages of conventional pressurized-type and submerged-type filtration apparatuses and a hollow fiber membrane module therefor. The filtration apparatus of the present invention comprises: a tank into which feed water is to be introduced, the tank comprising first and second inner step surfaces arranged opposite to each other; and a hollow fiber membrane module to be submerged in the feed water introduced in the tank, the hollow fiber membrane module comprising first and second headers and a hollow fiber membrane therebetween, wherein first and second ends of the first header are supported by the first and second inner step surfaces respectively.

Abstract translation: 公开了一种具有常规加压型和浸没式过滤装置及其中空纤维膜组件的优点的过滤装置。 本发明的过滤装置包括：供给水被引入的罐，所述罐包括彼此相对布置的第一和第二内台阶表面; 以及中空纤维膜组件，其浸没在引入到所述罐中的给水中，所述中空纤维膜组件包括第一和第二集管以及中间纤维膜，其中所述第一集管的第一和第二端由所述第一和第二集管支撑， 第二内部台阶表面。

公开(公告)号：US08520446B2

公开(公告)日：2013-08-27

申请号：US13535922

申请日：2012-06-28

Applicant: Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

Inventor： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC: G11C16/04

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US20130039124A1

公开(公告)日：2013-02-14

申请号：US13655666

申请日：2012-10-19

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20120269021A1

公开(公告)日：2012-10-25

申请号：US13535922

申请日：2012-06-28

Applicant: Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

Inventor： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC: G11C7/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US08218379B2

公开(公告)日：2012-07-10

申请号：US12318241

申请日：2008-12-23

Applicant: Yong-Jun Lee ,  Kwang-Jin Lee ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Woo-Yeong Cho ,  Hyun-Ho Choi ,  Hye Jin Kim

Inventor： Yong-Jun Lee ,  Kwang-Jin Lee ,  Taek-Sung Kim ,  Kwang-Ho Kim ,  Woo-Yeong Cho ,  Hyun-Ho Choi ,  Hye Jin Kim

IPC: G11C16/04

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/72

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。 控制电路被配置为存储至少一个擦除指示符。 擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。 控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

公开(公告)号：US08190851B2

公开(公告)日：2012-05-29

申请号：US12617758

申请日：2009-11-13

Applicant: Kwang-jin Lee ,  Young-kug Moon ,  Kwang-ho Kim

Inventor： Kwang-jin Lee ,  Young-kug Moon ,  Kwang-ho Kim

IPC: G06F12/00

CPC classification number: G06F12/0215 ,  G06F12/0238 ,  G06F2212/7203 ,  G11C7/103 ,  G11C13/0004 ,  G11C13/004 ,  Y02D10/13

Abstract: A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.

Abstract translation: 电阻可变存储器件包括电阻可变存储单元阵列，预取电阻可变存储单元阵列的读取数据的数据寄存器，从数据寄存器接收预取的读取数据并输出接收的数据的数据输出单元，以及 页面模式设置单元，其将第一页面模式和第二页面模式之一设置为页面模式。 在第一页面模式中，数据输出单元顺序地读取在数据寄存器中预取的读取数据，因为顺序地接收页面地址，而在第二页面模式中，数据输出单元顺序地读取在数据寄存器中预读取的读取数据 已经接收到多个页地址中的起始页地址。

公开(公告)号：US08189422B2

公开(公告)日：2012-05-29

申请号：US12929123

申请日：2011-01-03

Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC: G11C8/00

CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

公开(公告)号：US08159867B2

公开(公告)日：2012-04-17

申请号：US12395999

申请日：2009-03-02

Applicant: Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

Inventor： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US08116117B2

公开(公告)日：2012-02-14

申请号：US12632018

申请日：2009-12-07

Applicant: Woo-Yeong Cho ,  Ki-Sung Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Jun-Soo Bae

Inventor： Woo-Yeong Cho ,  Ki-Sung Kim ,  Du-Eung Kim ,  Kwang-Jin Lee ,  Jun-Soo Bae

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2211/5634

Abstract: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

Abstract translation: 公开了一种驱动多电平可变电阻存储器件的方法。 一种驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定电阻窗，预期电阻 窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少量的写入电流，以便改变可变电阻存储单元的电阻。