公开(公告)号：US20100328996A1

公开(公告)日：2010-12-30

申请号：US12729837

申请日：2010-03-23

Applicant: YEN-HAO SHIH ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung Hon Lam

Inventor： YEN-HAO SHIH ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung Hon Lam

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/1625 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

Abstract translation: 一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布 。 根据不同的晶体学，热学和电学条件以及不同的相变条件，使用“非恒定”浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

公开(公告)号：US20100328995A1

公开(公告)日：2010-12-30

申请号：US12715802

申请日：2010-03-02

Applicant: YEN-HAO SHIH ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung ,  Chung Hon Lam ,  Roger Cheek ,  Matthew J. Breitwisch ,  Bipin Rajendran

Inventor： YEN-HAO SHIH ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Hsiang-Lan Lung ,  Chung Hon Lam ,  Roger Cheek ,  Matthew J. Breitwisch ,  Bipin Rajendran

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C29/70 ,  G11C2213/79

Abstract: Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.

Abstract translation: 相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为 可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

公开(公告)号：US07852673B2

公开(公告)日：2010-12-14

申请号：US12561849

申请日：2009-09-17

Applicant: Hao-Ming Lien ,  Ming-Hsiu Lee

Inventor： Hao-Ming Lien ,  Ming-Hsiu Lee

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.

Abstract translation: 一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。 该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

公开(公告)号：US20100290293A1

公开(公告)日：2010-11-18

申请号：US12845064

申请日：2010-07-28

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C16/04

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US20100084624A1

公开(公告)日：2010-04-08

申请号：US12286874

申请日：2008-10-02

Applicant: Hsiang-Lan Lung ,  Chieh Fang Chen ,  Yen-Hao Shih ,  Ming Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

Inventor： Hsiang-Lan Lung ,  Chieh Fang Chen ,  Yen-Hao Shih ,  Ming Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L45/1226 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Abstract translation: 使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。 具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。 该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。 导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。 此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

公开(公告)号：US07564710B2

公开(公告)日：2009-07-21

申请号：US11742090

申请日：2007-04-30

Applicant: Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

Inventor： Thomas Happ ,  Jan Boris Philipp ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C11/56

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.

Abstract translation: 集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。 电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。 脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

公开(公告)号：US20090175071A1

公开(公告)日：2009-07-09

申请号：US11970348

申请日：2008-01-07

Applicant: MING-HSIU LEE ,  Bipin Rajendran ,  Chung Hon Lam

Inventor： MING-HSIU LEE ,  Bipin Rajendran ,  Chung Hon Lam

IPC: G11C11/00 ,  G11C29/00 ,  G01R31/28

CPC classification number: G11C29/50 ,  G11C13/0004 ,  G11C29/50008 ,  Y10T29/49004

Abstract: A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

Abstract translation: 用于测试集成电路存储器件的方法包括将测试脉冲序列应用于器件上的存储器单元，其中测试脉冲导致具有取决于测试脉冲的幅度的存储器单元的电流。 响应于测试脉冲的顺序测量存储器单元中的电阻。 从电阻测量中提取参数集，其包括至少一个数值系数，其模拟所测量的电阻对通过存储器单元的电流的振幅的依赖性。 提取的数值系数或系数与存储器件相关联，并用于控制制造操作。

公开(公告)号：US07495967B2

公开(公告)日：2009-02-24

申请号：US11601710

申请日：2006-11-20

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US07371604B2

公开(公告)日：2008-05-13

申请号：US11545988

申请日：2006-10-10

Applicant: Ming Hsiu Lee ,  Ruichen Liu

Inventor： Ming Hsiu Lee ,  Ruichen Liu

IPC: H01L21/00

CPC classification number: H01L27/2409 ,  H01L21/76885 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.

Abstract translation: 具有I形状和L形的接触结构以及制造I形和L形接触结构的方法被采用在半导体器件中，并且在某些情况下采用相变非易失性存储器件。 通过这些方法产生的I形和L形接触结构表现出相对较小的活性区域。 确定接触结构尺寸的方法采用能够创建易于重现的结果的常规半导体沉积和蚀刻处理步骤。

公开(公告)号：US20070296023A1

公开(公告)日：2007-12-27

申请号：US11425469

申请日：2006-06-21

Applicant: Chao-I Wu ,  Ming Hsiu Lee

Inventor： Chao-I Wu ,  Ming Hsiu Lee

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: A charge monitoring device is described for monitoring charging effect during semiconductor manufacturing. In a first aspect of the invention, a charge storage MOS memory structure comprises a substrate body, an oxide-nitride-oxide structure that overlays a top surface of the substrate and extends above the edges between a source region and a drain region, and a polygate formed over the oxide-nitride-oxide structure. When a charging source, such as UV light or plasma, is projected onto the charge storage device, the polygate of the charge storage device protects the nitride layer from charging effect The light source charges side walls of the oxide-nitride-oxide structure.

Abstract translation: 描述了用于监视半导体制造期间的充电效果的充电监视装置。 在本发明的第一方面中，电荷存储MOS存储器结构包括衬底主体，覆盖衬底的顶表面并在源极区域和漏极区域之间的边缘之上延伸的氧化物 - 氧化物 - 氧化物结构，以及 在氧化物 - 氮化物 - 氧化物结构上形成多晶硅。 当诸如UV光或等离子体的充电源投射到电荷存储装置上时，电荷存储装置的多晶硅保护氮化物层免受充电效应。光源对氧化物 - 氧化物 - 氧化物结构的侧壁充电。