公开(公告)号：US20040242171A1

公开(公告)日：2004-12-02

申请号：US10853654

申请日：2004-05-26

申请人： NEC Electronics Corporation

发明人： Akio Hosokawa ,  Kouichi Nishimura

IPC分类号： H03F003/16

CPC分类号： G09G3/20 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2370/08 ,  H03K5/1534 ,  H04L25/0272 ,  H04L25/0286

摘要： A transmitter circuit for use in a display device of the type having a transmission line consisting of aluminum or copper conductor formed on a glass substrate includes a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting and inverting output terminals; and an output-waveform control circuit for detecting the edge of the waveform of the input signal and responding by increasing the signal current temporarily.

摘要翻译： 用于具有形成在玻璃基板上的由铝或铜导体构成的传输线的类型的显示装置的发射机电路包括具有非反相输出端和反相输出端的驱动电路，用于输出信号 具有基于输入信号改变的环路方向的电流到非反相和反相输出端子; 以及输出波形控制电路，用于检测输入信号的波形的边缘并且通过临时增加信号电流来进行响应。

公开(公告)号：US20040227712A1

公开(公告)日：2004-11-18

申请号：US10835398

申请日：2004-04-30

申请人： NEC Corporation ,  NEC Electronics Corporation

发明人： Daigo Miyasaka ,  Takashi Nose

IPC分类号： G09G003/36

CPC分类号： G09G3/3696 ,  G09G3/20 ,  G09G3/2003 ,  G09G3/2011 ,  G09G3/2018 ,  G09G3/3648 ,  G09G2320/0276 ,  G09G2320/066 ,  G09G2320/103 ,  G09G2330/028 ,  G09G2360/16

摘要： A display, an image processing apparatus and an image processing method for producing excellent visual images while suppressing the accumulation of quantization errors related to increasingly complex digital image processing. Among a variety of image processing, processing which can be represented by look-up tables (LUT) such as constant number multiplication and constant number addition/subtraction is performed equivalently by changing reference values in a reference gray-level signal generator of a display. Thus, the operation of a digital image processing unit can be simplified, and there is obtained the display making the most use of the output dynamic range while suppressing the occurrence and accumulation of quantization errors.

摘要翻译： 一种用于在抑制与日益复杂的数字图像处理相关的量化误差的累积的同时产生优异的视觉图像的显示器，图像处理装置和图像处理方法。 在各种图像处理中，通过改变显示器的参考灰度级信号发生器中的参考值来等效地执行可以由诸如常数乘法和常数加法/减法的查找表（LUT）表示的处理。 因此，可以简化数字图像处理单元的操作，并且在抑制量化误差的发生和累积的同时，获得最大限度地利用输出动态范围的显示。

公开(公告)号：US20040225985A1

公开(公告)日：2004-11-11

申请号：US10830019

申请日：2004-04-23

申请人： NEC Electronics Corporation

发明人： Yoshiki Kashiwagi ,  Tetsuya Katoh

IPC分类号： G06F009/45 ,  G06F017/50

CPC分类号： G06F17/5045

摘要： To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing short-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.

摘要翻译： 为了设计具有由不同电源驱动的多个电路区域的芯片，准备要插入在电路区域之间的边界上的边界单元。 在使用设计工具创建逻辑电路网表后，边界单元插入边界。 边界单元连接在电路区域之间的信号传输路径上。 作为边界电路，使用抑制短路电流或漏电流的电路。 通过在单元库中准备边界单元，便于芯片设计。

公开(公告)号：US20040216389A1

公开(公告)日：2004-11-04

申请号：US10777089

申请日：2004-02-13

申请人： NEC ELECTRONICS CORPORATION ,  TOKYO MAGNETIC PRINTING CO., LTD

发明人： Yasuaki Tsuchiya ,  Toshiji Taiji ,  Tetsuyuki Itakura ,  Shin Sakurai ,  Kenichi Aoyagi ,  Tomoyuki Ito

IPC分类号： C09K003/14 ,  B24D003/02

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/3212

摘要： This invention relates to a chemical mechanical polishing slurry comprising polishing grains, ammonium nitrate as an oxidizing agent, 1,2,4-triazole as a polishing promoter for a copper metal film and water and having a pH within a range of 3 to 4. The polishing slurry is suitable for forming a damascene copper-based metal interconnection comprising a tantalumr-based metal as a barrier metal film material.

摘要翻译： 本发明涉及一种化学机械抛光浆料，其包括抛光颗粒，硝酸铵作为氧化剂，1,2,4-三唑作为铜金属膜和水的抛光促进剂，其pH值在3至4范围内。 抛光浆料适于形成包含钽基金属作为阻挡金属膜材料的镶嵌铜基金属互连。

公开(公告)号：US20040209424A1

公开(公告)日：2004-10-21

申请号：US10822676

申请日：2004-04-13

申请人： NEC ELECTRONICS CORPORATION

发明人： Junichi Suzuki ,  Kohji Kanamori

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L021/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A silicon layer doped with an impurity for a floating gate, a protective layer, a silicon nitride layer of a laminated hard mask and a first NSG layer are formed into a desired pattern, on which a second NSG layer is formed and left as a side wall. With the second NSG layer as a mask, the silicon nitride layer is etched. Using the remaining silicon nitride layer as a mask, the silicon layer is etched to form a silicon pattern whose surface is covered with a second protective layer, and the silicon nitride layer is etched out. Accordingly, it is possible to prevent a damage at the surface of the floating gate at the time of forming the floating gate using doped polysilicon.

摘要翻译： 掺杂有用于浮置栅极，保护层，层叠硬掩模和第一NSG层的氮化硅层的杂质的硅层形成为期望的图案，其上形成有第二NSG层并且作为侧面 壁。 以第二NSG层作为掩模，蚀刻氮化硅层。 使用剩余的氮化硅层作为掩模，蚀刻硅层以形成其表面被第二保护层覆盖的硅图案，并且蚀刻氮化硅层。 因此，可以防止在使用掺杂多晶硅形成浮置栅极时在浮栅的表面处的损坏。

公开(公告)号：US20040207445A1

公开(公告)日：2004-10-21

申请号：US10844555

申请日：2004-05-13

申请人： NEC Electronics Corporation

发明人： Takanori Saeki

IPC分类号： G06F001/04

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

公开(公告)号：US20040207443A1

公开(公告)日：2004-10-21

申请号：US10844552

申请日：2004-05-13

申请人： NEC Electronics Corporation

发明人： Takanori Saeki

IPC分类号： H03B019/00

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

公开(公告)号：US20040207442A1

公开(公告)日：2004-10-21

申请号：US10844549

申请日：2004-05-13

申请人： NEC Electronics Corporation

发明人： Takanori Saeki

IPC分类号： G06F001/04

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/133 ,  H03K5/14 ,  H04L7/0337

摘要： A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

摘要翻译： 一种用于消除整个时钟传播线路中的延迟差的时钟控制电路和方法。 与使用PLL或DLL电路的情况相比，电路规模减小。 定时平均电路10从方向反转时钟传播路径的前向路径111上的位置馈送时钟，适用于在其一端馈送输入时钟，并且从对应于输入时钟的返回路线112上的位置 位置在正向路径111上。这些时钟之间的定时差被平均以输出平均的定时差。

公开(公告)号：US20040201052A1

公开(公告)日：2004-10-14

申请号：US10812282

申请日：2004-03-30

申请人： NEC ELECTRONICS CORPORATION

发明人： Yasutaka Nakashiba

IPC分类号： H01L031/062

CPC分类号： H01L27/0629 ,  H01L27/0811 ,  H01L27/088

摘要： A semiconductor integrated circuit device includes a P type substrate. An N-channel MOS transistor, a P-channel MOS transistor, and an MOS type varactor element are provided in the upper surface of the P type substrate. A gate insulating film of the MOS type varactor element is thinner than gate insulating films of the N-channel MOS transistor and the P-channel MOS transistor. Also, a maximum gate voltage applied between a well terminal and a gate terminal of the MOS type varactor element is lower than a maximum gate voltage applied to the N-channel MOS transistor and the P-channel MOS transistor.

摘要翻译： 半导体集成电路器件包括P型衬底。 在P型基板的上表面设置有N沟道MOS晶体管，P沟道MOS晶体管和MOS型变容二极管元件。 MOS型变容二极管元件的栅极绝缘膜比N沟道MOS晶体管和P沟道MOS晶体管的栅极绝缘膜薄。 此外，施加在MOS型变容二极管元件的阱端子和栅极端子之间的最大栅极电压低于施加到N沟道MOS晶体管和P沟道MOS晶体管的最大栅极电压。

公开(公告)号：US20040189275A1

公开(公告)日：2004-09-30

申请号：US10801819

申请日：2004-03-17

申请人： NEC ELECTRONICS CORPORATION

发明人： Teru Yoneyama

IPC分类号： G05F003/16

CPC分类号： G05F3/262

摘要： A current drive circuit is provided with a bias generator and a current output unit; wherein the bias generator is provided with: p-channel MOS transistor, p-channel MOS transistor, and reference current source; and the current output unit is provided with: p-channel MOS transistor, switch means, p-channel MOS transistor, and output terminal.

摘要翻译： 电流驱动电路设有偏置发生器和电流输出单元; 其中所述偏置发生器设置有：p沟道MOS晶体管，p沟道MOS晶体管和参考电流源; 并且电流输出单元设置有：p沟道MOS晶体管，开关装置，p沟道MOS晶体管和输出端子。