公开(公告)号：US08934595B2

公开(公告)日：2015-01-13

申请号：US14156202

申请日：2014-01-15

Applicant: National Instruments Corporation

Inventor： I. Zakir Ahmed ,  Krishna Bharadwaj ,  Ramesh Krishnan ,  Vijaya Yajnanarayana

IPC: H04L7/033 ,  H04L7/00 ,  H03M1/12

CPC classification number: H04L7/033 ,  H03M1/1255 ,  H04L7/0087

Abstract: A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/TS′ of a receiver and an intended sample clock rate 1/TS. The receiver captures samples of a received baseband signal at the rate 1/TS′, operates on the captured samples to generate an estimate for the clock rate offset, and fractionally resamples the captured samples using the clock rate offset. The resampled data represents an estimate of baseband symbols transmitted by the transmitter. The action of operating on the captured samples involves computing an error vector signal and then estimating the clock rate offset using the error vector signal. The error vector signal may be computed in different ways depending on whether or not carrier frequency offset and carrier phase offset are assumed to be present in the received baseband signal.

Abstract translation: 用于操作接收机以便估计接收机的实际采样时钟速率1 / TS'与预期采样时钟速率1 / TS之间的偏移的低复杂度系统和方法。 接收机以速率1 / TS'捕获接收到的基带信号的采样，对捕获的采样进行操作，以产生时钟偏移量的估计，并且使用时钟速率偏移对所捕获的采样进行分数重新采样。 重采样的数据表示由发射机发射的基带符号的估计。 在捕获的样本上操作的动作包括计算误差矢量信号，然后使用误差矢量信号估计时钟偏移。 取决于载波频率偏移和载波相位偏移是否被假设为存在于接收基带信号中，可以以不同的方式计算误差向量信号。

公开(公告)号：US20140372660A1

公开(公告)日：2014-12-18

申请号：US13918435

申请日：2013-06-14

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: A PCIe subsystem may be coupled to a host by a system extender adapted to perform PCIe packet routing based on packet type. A first TLP (transport layer packet) type router may receive PCIe packets, and selectively route the PCIe packets according to the type of the packet through a corresponding path of at least two alternate paths. A second TLP type router may receive the routed packet through a first path if the PCIe packet was routed through the first path, and may receive the routed packet through a second path if the routed packet was routed through the second path. A non transparent bridge may be coupled between the first TLP type router block and the second TLP type router block along the second path, while the first path may be a pass-through path from the first TLP type router block to the second TLP type router block.

Abstract translation: PCIe子系统可以由适于基于分组类型执行PCIe分组路由的系统扩展器耦合到主机。 第一TLP（传输层分组）型路由器可以接收PCIe分组，并且根据分组的类型通过至少两个备选路径的对应路径选择性地路由PCIe分组。 如果PCIe分组通过第一路径路由，则第二TLP类型路由器可以经由第一路径接收路由分组，并且如果路由分组被路由通过第二路径，则可以通过第二路径接收路由分组。 第一TLP型路由器块和第二TLP型路由器块之间可以沿着第二路径耦合非透明桥，而第一路径可以是从第一TLP型路由器块到第二TLP型路由器的直通路径 块。

公开(公告)号：US20140372641A1

公开(公告)日：2014-12-18

申请号：US13918685

申请日：2013-06-14

Applicant: National Instruments Corporation

Inventor： Jonathan W. Hearn ,  Craig S. Jones ,  Robert D. Ross

IPC: G06F13/40

CPC classification number: G06F13/4045 ,  G06F9/5077 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract translation: 选择性透明的桥接器有助于将PCI设备作为PCI至PCI桥接器呈现给主机，但是选择性地将硬件与主机总线隔离并隔离。 PCI配置可以通过标准的PCI Express配置机制来实现，但不是直接配置设备，而是选择性透明的桥接器中的配置处理器可以拦截来自主机的配置数据包，并创建一个虚拟配置，以改变总线拓扑的显示方式 主人。 设备由配置处理器选择性地隐藏和管理，导致简化的复杂性和总线深度。 由于选择性透明的桥接器作为透明桥显示给主机，因此不需要特殊的驱动程序或资源预分配，尽管选择性透明的桥完全支持特殊驱动程序和/或资源预分配。 因此，位于/连接在桥下游的设备因此可以与未修改的驱动器一起工作。

公开(公告)号：US20140359590A1

公开(公告)日：2014-12-04

申请号：US14063130

申请日：2013-10-25

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Jeffrey L. Kodosky ,  Hugo A. Andrade ,  Brian Keith Odom ,  Cary Paul Butler ,  Brian C. MacCleery ,  James C. Nagle ,  J. Marcus Monroe ,  Alexandre M. Barp

IPC: G06F9/45

CPC classification number: G06F8/34 ,  G06F7/483 ,  G06F8/451 ,  G06F2207/48

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract translation: 用于配置异构硬件组件系统的系统和方法，包括至少一个：可编程硬件元件（PHE），数字信号处理器（DSP）核心和可编程通信元件（PCE）。 创建包括浮点数学功能并且用于在系统上进行分布式部署的程序，例如图形程序（GP）。 用于部署到相应硬件组件的程序的各个部分被自动确定。 在至少一个PHE和至少一个DSP核之间实现通信功能并且被目标用于部署到至少一个PCE的程序代码被自动生成。 从程序和代码生成至少一个硬件配置程序（HCP），包括将程序的各个部分和用于部署的程序代码编译到各个硬件组件。 HCP可以部署到系统以便并发执行程序。

公开(公告)号：US20140358469A1

公开(公告)日：2014-12-04

申请号：US14295443

申请日：2014-06-04

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Christopher F. Graf ,  Ryan P. Verret ,  Joseph H. DiGiovanni ,  David E. Klipec ,  Dustyn K. Blasig ,  Jeronimo Mota ,  Kunal H. Patel ,  Duncan G. Hudson, III ,  Brian K. Odom

IPC: G01D11/00

CPC classification number: G01D11/00 ,  G06F9/4411 ,  G06F11/273 ,  G06F17/5054

Abstract: System and method for extending programmable device functionality while preserving functionality of the device driver and driver IP. User input may be received specifying functionality of custom IP for a programmable measurement device with standard driver IP. The custom IP may be generated accordingly, and may be deployable to the programmable measurement device. During operation the custom IP may communicate directly with the standard driver IP and may provide custom functionality of the programmable measurement device while preserving functionality of the standard driver IP on the programmable measurement device and the standard device driver.

Abstract translation: 用于扩展可编程设备功能的系统和方法，同时保留设备驱动程序和驱动程序IP的功能。 可以接收用户输入，指定具有标准驱动程序IP的可编程测量设备的自定义IP的功能。 可以相应地生成定制IP，并且可以部署到可编程测量设备。 在操作期间，定制IP可以直接与标准驱动器IP通信，并且可以提供可编程测量设备的定制功能，同时在可编程测量设备和标准设备驱动器上保持标准驱动器IP的功能。

公开(公告)号：US08868021B1

公开(公告)日：2014-10-21

申请号：US13857481

申请日：2013-04-05

Applicant: National Instruments Corporation

Inventor： Alexander Feldman

IPC: H04B1/26 ,  H04B1/04 ,  H01P5/10 ,  H04B1/18

CPC classification number: H01P5/1015 ,  H01P1/213 ,  H03D7/02

Abstract: In some embodiments, a system may include a passive uniplanar single-balanced millimeter-wave mixer. In some embodiments, a three-port diode-tee IC forming a mixer core is coupled between an end of a slotline balun and a second coplanar balun. The operational bandwidth of a mixer structure is enhanced by optimizing the distance between the mixer diode-tee core and the back-short circuits. The frequency separation of LO and IF signals may be accomplished by means of stand-alone three-port filter-diplexer device. The system may allow wider than a frequency octave operational bandwidth for a frequency converter device all the way into millimeter wave frequencies at the same time as supporting the operational bandwidth for baseband IF signal over more than six frequency octaves. In some embodiments, the system may accomplish a 500 MHz to 34.5 GHz continuous IF bandwidth with RF signal sweeping from 33 GHz to 67 GHz and local oscillator at 67.5 GHz fixed frequency.

Abstract translation: 在一些实施例中，系统可以包括无源单面平衡毫米波混频器。 在一些实施例中，形成混频器核心的三端口二极管T形IC耦合在槽线平衡 - 不平衡转换器的一端和第二共面平衡 - 不平衡转换器之间。 混频器结构的工作带宽通过优化混频二极管三通芯与后短路之间的距离来增强。 LO和IF信号的频率分离可以通过独立的三端口滤波器 - 双工器件来实现。 该系统可以允许频率转换器装置的频率倍频程宽度大于毫米波频率，同时支持超过六个频率八度的基带IF信号的操作带宽。 在一些实施例中，该系统可以实现从33GHz到67GHz的RF信号扫描的500MHz至34.5GHz的连续IF带宽，以及固定频率为67.5GHz的本地振荡器。

公开(公告)号：US08862795B2

公开(公告)日：2014-10-14

申请号：US14026007

申请日：2013-09-13

Applicant: National Instruments Corporation

Inventor： Rafael Castro Scorsi

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/16 ,  G06F5/06 ,  G06F5/16 ,  G06F13/28

CPC classification number: G06F5/065 ,  G06F5/16 ,  G06F13/1647 ,  G06F13/28

Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes first and second memory banks. A first waveform is stored in chunks alternating between successive buffers in the first and second memory banks, and concurrently, the first and second chunks may be transferred to first and second FIFOs, respectively, which may be accumulated with respective first and second chunks of a second waveform into the first and second memory banks. This process may be repeated for respective successive pairs of the first and second waveforms, where the first and second memory banks and FIFOs are used in an alternating manner, and further, to accumulate additional waveforms, where previously stored (and accumulated) waveform data are accumulated chunkwise with successive additional waveform data, and where at least some of the accumulation is performed concurrently with waveform data transfers to and from the memory banks and FIFOs.

Abstract translation: 用于硬件实现的波形数据累积的系统和方法。 提供了包括第一和第二存储体的数字转换器。 第一波形以第一和第二存储体中的连续缓冲器之间交替存储的块中存储，并且同时，第一和第二块可以分别传送到第一和第二FIFO，其可以用相应的第一和第二块 第二波形进入第一和第二存储体。 可以针对第一和第二波形的相应连续对重复该过程，其中以交替方式使用第一和第二存储体和FIFO，并且还累积额外的波形，其中预先存储（和累积）波形数据是 与连续的附加波形数据块块累积，并且其中至少一些累积与到存储器组和FIFO的波形数据传输同时执行。

公开(公告)号：US20140286382A1

公开(公告)日：2014-09-25

申请号：US14220284

申请日：2014-03-20

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Stephen L. Dark

IPC: H04B17/00

CPC classification number: H04L25/08 ,  H04B17/104 ,  H04B17/11 ,  H04B17/21 ,  H04B17/309 ,  H04B17/373 ,  H04B17/391 ,  H04L1/248

Abstract: Systems and methods for measuring transmitter and/or receiver I/Q impairments are disclosed, including iterative methods for measuring transmitter I/Q impairments using shared local oscillators, iterative methods for measuring transmitter I/Q impairments using intentionally-offset local oscillators, and methods for measuring receiver I/Q impairments. Also disclosed are methods for computing I/Q impairments from a sampled complex signal, methods for computing DC properties of a signal path between the transmitter and receiver, and methods for transforming I/Q impairments through a linear system.

Abstract translation: 公开了用于测量发射机和/或接收机I / Q损伤的系统和方法，包括使用共享本地振荡器测量发射机I / Q损伤的迭代方法，使用有意偏移的本地振荡器测量发射机I / Q损伤的迭代方法，以及方法 用于测量接收机I / Q损伤。 还公开了用于从采样的复信号计算I / Q损伤的方法，用于计算发射机和接收机之间的信号路径的DC特性的方法，以及通过线性系统变换I / Q损伤的方法。

公开(公告)号：US20140257735A1

公开(公告)日：2014-09-11

申请号：US14281030

申请日：2014-05-19

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Tamir E. Moran ,  Jatinderjit S. Bains ,  Daniel S. Wertz

IPC: G01R35/00

CPC classification number: G01R35/005 ,  G01R19/2516

Abstract: A user obtains a set of modules, inserts them into slots of a chassis, and interconnects the modules to form a modular instrument. A signal path extends through the modules. To support calibration of the signal path, a first of the modules (or the chassis or a calibration module) includes a calibration signal generator. A computer directs the first module to apply the calibration signal from the generator to the signal path, and measures the power (or amplitude) of the output of the signal path. The computer reads a factory-measured value A of the calibration signal amplitude from a memory of the first module (or the chassis or the calibration module). The value A and the measured output power of the signal path are used to determine a gain of the signal path. The system compensates for that gain when the signal path is used to measure live operational signals.

Abstract translation: 用户获取一组模块，将其插入到机箱的插槽中，并将模块互连以形成模块化仪器。 信号路径延伸穿过模块。 为了支持信号路径的校准，第一个模块（或机箱或校准模块）包括校准信号发生器。 计算机引导第一模块将来自发生器的校准信号施加到信号路径，并且测量信号路径的输出的功率（或幅度）。 计算机从第一个模块（或机箱或校准模块）的存储器读取校准信号振幅的出厂测量值A. 使用值A和信号路径的测量输出功率来确定信号路径的增益。 当信号路径用于测量实时操作信号时，系统补偿该增益。

公开(公告)号：US20140241410A1

公开(公告)日：2014-08-28

申请号：US14186727

申请日：2014-02-21

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Stephen L. Dark

IPC: H04B1/12

CPC classification number: H04B1/123 ,  H04B17/21 ,  H04L27/364

Abstract: The first and second outputs of a signal generation system are coupled to the first and second inputs of a signal digitizing system via respective electrical conductors. A controller directs the generation system to generate a first calibration signal, and the digitizing system responsively captures a first set of vector samples. The conductors are then reconfigured so they connect the first and second outputs of the generation system respectively to the second and first inputs of the digitization system. The controller then directs the generation system to generate a second calibration signal, and the digitizing system responsively captures a second set of vector samples. The controller or other processing agent computes gain and/or phase impairments using the first and second vector sample sets. Digital filter parameters may be computed based on the computed impairment(s), and used to correct the impairment(s) of the generation system and/or the digitizing system.

Abstract translation: 信号发生系统的第一和第二输出通过相应的电导体耦合到信号数字化系统的第一和第二输入端。 控制器指示生成系统生成第一校准信号，并且数字化系统响应地捕获第一组向量样本。 然后重新配置导体，使得它们将生成系统的第一和第二输出分别连接到数字化系统的第二和第一输入端。 然后，控制器引导生成系统生成第二校准信号，并且数字化系统响应地捕获第二组矢量样本。 控制器或其他处理代理使用第一和第二向量样本集计算增益和/或相位损伤。 可以基于所计算的损伤来计算数字滤波器参数，并且用于校正发电系统和/或数字化系统的损害。