公开(公告)号：US20020074607A1

公开(公告)日：2002-06-20

申请号：US10077288

申请日：2002-02-15

Applicant: STMicroelectronics, S.r.I.

Inventor： Loris Vendrame ,  Paolo Ghezzi

IPC: H01L029/94

CPC classification number: H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 1016 and 1017 atoms/cm3.

Abstract translation: 双极晶体管是通过制造CMOS非易失性存储器件的工艺生产的，并且是集成电路的一部分。 集成电路包括具有第一导电类型的半导体衬底，形成在所述衬底中的PMOS晶体管，形成在所述衬底中的NMOS晶体管和双极晶体管。 所述双极晶体管包括：具有从所述双极晶体管的表面设置在规定深度的第二导电类型的掩埋半导体层，具有与所述掩埋半导体层直接接触的第二导电类型的隔离半导体区域， 用于限定所述衬底的一部分，形成基部区域; 形成在具有第二导电类型的所述基极区内的发射极区域，形成在具有第一导电类型的所述基极区域内的所述晶体管的基极接触区域，形成在具有第二导电类型的所述隔离半导体区域内的集电极接触区域 ，其中所述碱性区域的掺杂浓度为1016至1017原子/ cm3。

公开(公告)号：US20020020872A1

公开(公告)日：2002-02-21

申请号：US09976484

申请日：2001-10-12

Applicant: STMicroelectronics S.r.I.

Inventor： Carlo Cremonesi ,  Bruno Vajana ,  Roberta Bottini ,  Giovanna Dalla Libera

IPC: H01L029/788 ,  H01L029/76 ,  H01L029/792

CPC classification number: H01L27/11521 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

Abstract translation: 一种工艺形成了结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其中两个自对准多晶硅层具有存储晶体管和相关选择晶体管，该半导体材料包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中，形成栅极氧化物层并限定栅极氧化物层中包括的隧道氧化物区域，沉积并部分地限定形成多晶硅互连层的第一多晶硅层，并至少除去多晶硅绝缘层 在电路晶体管处沉积第二多晶硅层选择性地蚀刻掉电池处的第二多晶硅层，以及在电路晶体管处的第一和第二多晶硅层，并且选择性地蚀刻离开电池的多晶硅间介电层和第一多晶硅层。 在形成之后并且在部分地限定第一多晶硅层之前，该工艺至少在浮栅存储晶体管的沟道区域处注入以调整晶体管阈值。

公开(公告)号：US20020018390A1

公开(公告)日：2002-02-14

申请号：US09909467

申请日：2001-07-19

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Lorenzo Bedarida ,  Mauro Sali ,  Simone Bartoli

IPC: G11C005/14

CPC classification number: G11C16/30

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

公开(公告)号：US20010036115A1

公开(公告)日：2001-11-01

申请号：US09817804

申请日：2001-03-26

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC: G11C007/00

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

Abstract: A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

Abstract translation: 闪存存储器被组织在多个物理扇区中，这些物理扇区可被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。

公开(公告)号：US20240429928A1

公开(公告)日：2024-12-26

申请号：US18824653

申请日：2024-09-04

Applicant: STMicroelectronics S.r.I.

Inventor： Agatino Massimo Maccarrone ,  Antonino Conte ,  Francesco Tomaiuolo ,  Michelangelo Pisasale ,  Marco Ruta

IPC: H03M1/06

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

公开(公告)号：US20240061025A1

公开(公告)日：2024-02-22

申请号：US18493494

申请日：2023-10-24

Applicant: STMicroelectronics S.r.I

Inventor： Paolo Angelini

IPC: G01R19/25 ,  G01R15/14

CPC classification number: G01R19/25 ,  G01R15/146

Abstract: In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.

公开(公告)号：US20230361727A1

公开(公告)日：2023-11-09

申请号：US18308850

申请日：2023-04-28

Applicant: STMicroelectronics S.r.I.

Inventor： Gaetano Cosentino

IPC: H03G3/30 ,  H03F3/19

CPC classification number: H03F3/19 ,  H03G3/30 ,  H03F2200/451 ,  H03G2201/103

Abstract: A circuit includes an amplifier and a feedback network coupled between the input and the output of the amplifier. The feedback network includes a plurality of parallel coupled branches, each branch having a first selection switch coupled to the input, a second selection switch coupled to the output, and an impedance between the first and second selection switches. Each branch includes a plurality of signal feedback paths coupled in parallel, each having a tuning switch coupled between the first selection switch and the second selection switch of that branch. A control unit is coupled to the feedback network and configured to vary a gain of the amplifier by selectively placing the first and second selection switches of each branch in a conductive state or a non-conductive state and selectively activating respective tuning switches of any branch having first and second selection switches in the conductive state.

公开(公告)号：US20230130268A1

公开(公告)日：2023-04-27

申请号：US17933972

申请日：2022-09-21

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Ruta ,  Antonino Conte ,  Michelangelo Pisasale ,  Agatino Massimo Maccarrone ,  Francesco Tomaiuolo

IPC: G05F1/575 ,  H03K5/24 ,  H03K5/05

Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

公开(公告)号：US11595039B2

公开(公告)日：2023-02-28

申请号：US17658016

申请日：2022-04-05

Applicant: STMicroelectronics S.r.I.

Inventor： Noemi Gallo ,  Edoardo Botti

IPC: H03K17/00 ,  H03K17/56 ,  H03K19/20 ,  H03K17/687

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

公开(公告)号：US20220337236A1

公开(公告)日：2022-10-20

申请号：US17658016

申请日：2022-04-05

Applicant: STMicroelectronics S.r.I.

Inventor： Noemi Gallo ,  Edoardo Botti

IPC: H03K17/56 ,  H03K19/20

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.