公开(公告)号：US20050106897A1

公开(公告)日：2005-05-19

申请号：US10832952

申请日：2004-04-27

申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8234 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

公开(公告)号：US20050051835A1

公开(公告)日：2005-03-10

申请号：US10849219

申请日：2004-05-20

申请人： Sung-Taeg Kang ,  Seong-Gyun Kim

发明人： Sung-Taeg Kang ,  Seong-Gyun Kim

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： An electrically erasable and programmable read only memory (EEPROM) device may include: a gate oxide layer on a semiconductor substrate, the gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness and the third thickness being thinner than the first thickness; a floating junction region formed under a portion of the gate oxide layer in the semiconductor substrate; and a floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively, on the gate oxide layer.

摘要翻译： 电可擦除和可编程只读存储器（EEPROM）器件可以包括：半导体衬底上的栅氧化层，栅氧化层包括第一厚度的第一段，第二厚度的第二段和隧道第三段 所述第二厚度比所述第一厚度厚，所述第三厚度比所述第一厚度薄; 形成在所述半导体衬底中的所述栅极氧化物层的一部分下的浮置结区域; 以及分别依次形成在栅极氧化物层上的浮置栅极，绝缘层图案和控制栅极。

公开(公告)号：US06794711B2

公开(公告)日：2004-09-21

申请号：US10620025

申请日：2003-07-14

申请人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

发明人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： Non-volatile memory devices according to embodiments of the invention can include, for example, a semiconductor substrate, a source region, a drain region, an impurity region, a vertical structure, a control gate insulating layer, a control gate electrode, a gate insulating layer, and a gate electrode. The impurity region is in a floating state between the source region and the drain region. The vertical structure is formed of a tunneling layer, a charge trapping layer, and a blocking layer sequentially stacked between the source region and the impurity region. The control gate insulating layer is between the source region and the impurity region and adjacent to the vertical structure. The control gate electrode is formed on the vertical structure and the control gate insulating layer. The gate insulating layer is between the impurity region and the drain region. The gate electrode is formed on the gate insulating layer.

摘要翻译： 根据本发明的实施例的非易失性存储器件可以包括例如半导体衬底，源极区，漏极区，杂质区，垂直结构，控制栅极绝缘层，控制栅电极，栅极 绝缘层和栅电极。 杂质区域在源极区域和漏极区域之间处于浮置状态。 垂直结构由依次层叠在源极区域和杂质区域之间的隧道层，电荷俘获层和阻挡层形成。 控制栅极绝缘层位于源极区域和杂质区域之间并且与垂直结构相邻。 控制栅电极形成在垂直结构和控制栅极绝缘层上。 栅极绝缘层位于杂质区域和漏极区域之间。 栅电极形成在栅绝缘层上。

公开(公告)号：US09318568B2

公开(公告)日：2016-04-19

申请号：US14491551

申请日：2014-09-19

申请人： Asanga H. Perera ,  Sung-Taeg Kang

发明人： Asanga H. Perera ,  Sung-Taeg Kang

IPC分类号： H01L29/76 ,  H01L29/423 ,  H01L27/115 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/42348 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32139 ,  H01L27/11534 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545

摘要： A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.

摘要翻译： 制造半导体器件的方法包括在半导体器件的非易失性存储器区域中形成存储栅极结构，其中存储栅极结构包括通过电荷存储层与第二栅极分离的第一栅极。 逻辑门结构形成在半导体器件的逻辑区域中。 至少在金属电极部分上形成硬掩模。 选择性地蚀刻非易失性存储区域，使得在第一栅极中形成第一凹部，在第二栅极中形成第二凹部。

公开(公告)号：US09252246B2

公开(公告)日：2016-02-02

申请号：US13972372

申请日：2013-08-21

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42332

摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

摘要翻译： 制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。 通过沉积保形层，接着进行回蚀而形成控制栅极。 图案化的蚀刻导致将电荷存储层的一部分留在选择栅极上并在控制栅极之下并且从逻辑区域去除电荷存储层。 形成在逻辑区域中的逻辑门结构具有被绝缘层包围的金属功函数。

公开(公告)号：US09165652B2

公开(公告)日：2015-10-20

申请号：US13589249

申请日：2012-08-20

申请人： Sung-Taeg Kang ,  Cheong M. Hong

发明人： Sung-Taeg Kang ,  Cheong M. Hong

IPC分类号： H01L29/792 ,  H01L29/423 ,  G11C16/04 ,  H01L21/28 ,  H01L29/788

CPC分类号： G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.

摘要翻译： 公开了具有选择侧壁金属硅化物区域的分离栅极非易失性存储器（NVM）单元以及相关的制造方法。 间隔蚀刻处理步骤用于暴露选择栅极的侧壁部分。 然后在选择栅极的这些侧壁部分内形成金属硅化物区域。 此外，金属硅化物区域也可以形成在选择栅极的顶部。 此外，选择栅极也可以形成有一个或多个凹口。 通过扩大金属硅化物区域的尺寸以包括选择栅极的侧壁部分，分离栅极NVM阵列的选择栅极字线（例如，多晶硅）电阻降低，与选择栅极的电接触被改善，并且性能 的选择栅NVN单元。

公开(公告)号：US20140319593A1

公开(公告)日：2014-10-30

申请号：US13873917

申请日：2013-04-30

申请人： Jane A. YATER ,  Cheong Min HONG ,  Sung-Taeg KANG ,  Ronald J. SYZDEK

发明人： Jane A. YATER ,  Cheong Min HONG ,  Sung-Taeg KANG ,  Ronald J. SYZDEK

IPC分类号： H01L27/115 ,  H01L29/423

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332

摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

摘要翻译： 分割门存储器阵列包括具有存储器单元的第一行; 具有存储单元的第二行，其中所述第二行与所述第一行相邻; 和多个段。 每个段包括第一行的第一多个存储单元，第二行的第二多个存储单元，形成第一多个存储单元的每个存储单元的控制栅极的第一控制栅极部分， 控制栅极部分，其形成第二多个存储单元的每个存储单元的控制栅极。 第一控制栅极部分和第二控制栅极部分会聚到多个段的相邻段之间的单个控制栅极部分。

公开(公告)号：US08724399B2

公开(公告)日：2014-05-13

申请号：US13451876

申请日：2012-04-20

申请人： Brian A. Winstead ,  Sung-Taeg Kang

发明人： Brian A. Winstead ,  Sung-Taeg Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348

摘要： Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths.

摘要翻译： 公开了使用选择栅极擦除电压来擦除分裂门非易失性存储器（NVM）单元的方法和系统，其被调整以将选择栅极减小到控制门分解故障。 经调整的选择栅极擦除电压在选择栅极上提供偏置电压，其被配置为具有与在擦除操作期间施加的控制栅极擦除电压相同的极性，并且与读取操作期间施加的选择栅极读取电压不同。 某些另外的实施例使用用于分离栅NVM单元的离散电荷存储层，并且包括具有取决于控制栅介质层宽度的间隙介电层厚度的分裂栅极NVM单元。

公开(公告)号：US20140050029A1

公开(公告)日：2014-02-20

申请号：US13589249

申请日：2012-08-20

申请人： Sung-Taeg Kang ,  Cheong M. Hong

发明人： Sung-Taeg Kang ,  Cheong M. Hong

IPC分类号： G11C16/08 ,  H01L29/788 ,  H01L21/336

CPC分类号： G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.

摘要翻译： 公开了具有选择侧壁金属硅化物区域的分离栅极非易失性存储器（NVM）单元以及相关的制造方法。 间隔蚀刻处理步骤用于暴露选择栅极的侧壁部分。 然后在选择栅极的这些侧壁部分内形成金属硅化物区域。 此外，金属硅化物区域也可以形成在选择栅极的顶部。 此外，选择栅极也可以形成有一个或多个凹口。 通过扩大金属硅化物区域的尺寸以包括选择栅极的侧壁部分，分离栅极NVM阵列的选择栅极字线（例如，多晶硅）电阻降低，与选择栅极的电接触被改善，并且性能 的选择栅NVN单元。

公开(公告)号：US20130279267A1

公开(公告)日：2013-10-24

申请号：US13451876

申请日：2012-04-20

申请人： Brian A. Winstead ,  Sung-Taeg Kang

发明人： Brian A. Winstead ,  Sung-Taeg Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348

摘要： Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths.

摘要翻译： 公开了使用选择栅极擦除电压来擦除分裂门非易失性存储器（NVM）单元的方法和系统，其被调整以将选择栅极减小到控制门分解故障。 经调整的选择栅极擦除电压在选择栅极上提供偏置电压，其被配置为具有与在擦除操作期间施加的控制栅极擦除电压相同的极性，并且与读取操作期间施加的选择栅极读取电压不同。 某些另外的实施例使用用于分离栅NVM单元的离散电荷存储层，并且包括具有取决于控制栅介质层宽度的间隙介电层厚度的分裂栅极NVM单元。