公开(公告)号：US09685339B2

公开(公告)日：2017-06-20

申请号：US13873917

申请日：2013-04-30

申请人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Ronald J. Syzdek

发明人： Jane A. Yater ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Ronald J. Syzdek

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11521

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332

摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

公开(公告)号：US09397176B2

公开(公告)日：2016-07-19

申请号：US14446796

申请日：2014-07-30

申请人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

发明人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

IPC分类号： H01L21/8239 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08 ,  H01L29/41

CPC分类号： H01L29/42328 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

摘要翻译： 第一掺杂区从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。

公开(公告)号：US09219167B2

公开(公告)日：2015-12-22

申请号：US14135142

申请日：2013-12-19

申请人： Jacob T. Williams ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

发明人： Jacob T. Williams ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

公开(公告)号：US20150035034A1

公开(公告)日：2015-02-05

申请号：US13954205

申请日：2013-07-30

申请人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

发明人： BRIAN A. WINSTEAD ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Jane A. Yater

IPC分类号： H01L29/66 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

摘要翻译： 制造半导体结构的方法使用具有第一类型的背景掺杂的衬底。 栅极结构在衬底上具有栅极电介质，栅极电介质上具有选择栅极层。 使用第二类型的掺杂剂，将与第一端相邻的衬底的第一部分进行植入。 在将任何掺杂剂注入到成为第二类型的第一掺杂区域的第一部分的背景掺杂之前，注入之前。 NVM栅极结构具有选择栅极，在第一掺杂区域上具有第一部分的存储层以及存储层上的控制栅极。 以与第一类型的掺杂剂非垂直的角度植入在选择栅极下形成深掺杂区域。 与第二种类型的掺杂剂一起植入形成源/漏扩展。

公开(公告)号：US20150001612A1

公开(公告)日：2015-01-01

申请号：US13928666

申请日：2013-06-27

申请人： CHEONG MIN HONG ,  SUNG-TAEG KANG ,  JANE A. YATER

发明人： CHEONG MIN HONG ,  SUNG-TAEG KANG ,  JANE A. YATER

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。

公开(公告)号：US08679912B2

公开(公告)日：2014-03-25

申请号：US13362697

申请日：2012-01-31

申请人： Sung-Taeg Kang ,  Gowrishankar L. Chindalore ,  Brian A. Winstead ,  Jane A. Yater

发明人： Sung-Taeg Kang ,  Gowrishankar L. Chindalore ,  Brian A. Winstead ,  Jane A. Yater

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42332

摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.

摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。

公开(公告)号：US08329543B2

公开(公告)日：2012-12-11

申请号：US13085230

申请日：2011-04-12

申请人： Sung-Taeg Kang ,  Jane A. Yater

发明人： Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L21/336

CPC分类号： H01L29/42348 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66833

摘要： A method is provided for forming a semiconductor device having nanocrystals. The method includes: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a first plurality of nanocrystals on the first insulating layer; forming a second insulating layer over the first plurality of nanocrystals; implanting a first material into the second insulating layer; and annealing the first material to form a second plurality of nanocrystals in the second insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.

摘要翻译： 提供了一种形成具有纳米晶体的半导体器件的方法。 该方法包括：提供衬底; 在所述基板的表面上形成第一绝缘层; 在所述第一绝缘层上形成第一多个纳米晶体; 在所述第一多个纳米晶体上形成第二绝缘层; 将第一材料注入第二绝缘层; 以及退火所述第一材料以在所述第二绝缘层中形成第二多个纳米晶体。 该方法可用于为具有更大纳米晶体密度的非易失性存储器提供电荷存储层。

公开(公告)号：US20150179816A1

公开(公告)日：2015-06-25

申请号：US14135142

申请日：2013-12-19

申请人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

发明人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

IPC分类号： H01L29/792 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

公开(公告)号：US09006093B2

公开(公告)日：2015-04-14

申请号：US13928666

申请日：2013-06-27

申请人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。

公开(公告)号：US20120126309A1

公开(公告)日：2012-05-24

申请号：US12951862

申请日：2010-11-22

申请人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

发明人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

IPC分类号： H01L29/68 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

摘要： A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.

摘要翻译： 在NVM器件和逻辑器件的图案化和蚀刻期间，在NVM隔离区域中形成特征，使得该特征与逻辑器件的高度基本相等，并且被明确地限定，使得其不会引起缺陷信号。 第一导电层形成在衬底上。 图案化第一导电层以在NVM区域和隔离区域的至少一部分中露出衬底的至少一部分。 在第一导电层，暴露的衬底和暴露的隔离区上方形成NVM电介质堆叠，并且在NVM电介质叠层上形成第二导电层。 图案化第一和第二导电层和NVM电介质叠层以形成NVM区域中的NVM单元的第一栅极和第二栅极以及隔离区域上的特征。 该特征包括第一导电层的一部分，与第一导电层的该部分的第一侧壁相邻的NVM电介质堆叠的一部分以及邻近NVM电介质叠层部分的第二导电层的一部分。